TLE7230R Infineon Technologies, TLE7230R Datasheet - Page 5
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
TLE7230R
Manufacturer Part Number
TLE7230R
Description
IC SW SMART OCTAL LOWSIDE PDSO36
Manufacturer
Infineon Technologies
Type
Low Sider
Specifications of TLE7230R
Input Type
SPI
Number Of Outputs
8
On-state Resistance
800 mOhm
Current - Peak Output
2A
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
DSO-36
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output / Channel
-
Other names
SP000067170
SP000311685
TLE7230R
TLE7230RNT
TLE7230RT
TLE7230RT
TLE7230RTR
TLE7230RXT
SP000311685
TLE7230R
TLE7230RNT
TLE7230RT
TLE7230RT
TLE7230RTR
TLE7230RXT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TLE7230R
Manufacturer:
INFINEON
Quantity:
5 510
Part Number:
TLE7230R
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Company:
Part Number:
TLE7230R1
Manufacturer:
SEMTECH
Quantity:
471
Electrical Characteristics cont.
Parameter and Conditions
V
T
(unless otherwise specified)
5. Diagnostic Functions
Open Load Detection Voltage
Output Pull Down Current
Fault Delay Time
Overload switch off delay time
Short to Ground Detection Voltage
Short to Ground Detection Current
Overload Threshold Current
Overtemperature Shutdown Threshold
Hysteresis
6. SPI-Timing (for V
Serial Clock Frequency (depending on SO load)
Serial Clock Period (1/fclk)
Serial Clock High Time
Serial Clock Low Time
Enable Lead Time (falling edge of CS to rising edge of
Enable Lag Time (falling edge of CLK to rising edge ofCS)
Data Setup Time (required time SI to falling of CLK)
Data Hold Time (falling edge of CLK to SI)
Disable Time
Transfer Delay Time
(CS high time between two accesses)
Data Valid Time (for V
Data Valid Time (for V
2
3
V2.0
This parameter is not subject to production test. Specified by design.
This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay
j
time has to be extended to the maximum fault delay time t
S
= - 40 °C to + 150 °C ; Reset = H
= 4.5 to 5.5 V; V
2
2
VDO
3
VDO
VDO
VDO
= 3.0 to 5.5V;
= 4.5V to 5.5V)
= 4.5V to 5.5V)
= 3.0V to 3.6V)
2,4
C
C
C
C
C
C
L
L
L
L
L
L
Page
= 50 pF
= 100 pF
= 220 pF
= 50 pF
= 100 pF
= 220 pF
d(fault)max
CLK
5
2
2
D a t a S h e e t T L E 7 2 3 0 R
2
2
2
2
) t
= 200µs.
Symbol
V
I
t
T
V
I
I
T
T
f
t
t
t
t
t
t
t
t
t
t
PD(OL)
d(fault)
SHG
D(OVL) 1...8
SCK
p(SCK)
SCKH
SCKL
lead
lag
SU
H
DIS
dt
valid
valid
d(off)
th(sd)
hys
DS(OL)
DS(SHG)
Values
V
V
50
50
10
-50
1
170
--
DC
200
50
50
250
250
20
20
--
200
--
--
--
--
--
--
min
S
S
-3.4 V
-2.5 V
90
100
-100
--
10
--
--
--
--
--
---
--
--
--
--
S
S
typ
-2
-3.0 V
V
100
120
150
100
140
240
150
200
50
-150
2
200
--
5
--
--
--
--
--
--
--
150
--
max
S
S
-1.3 V
-2.6 V
2005-10-05
Unit
µA
µs
µA
A
°C
K
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs