IR22141SS International Rectifier, IR22141SS Datasheet - Page 19

• Manufacturer Part Number: IR22141SS
• Description: IC DRIVER HALF BRIDGE SGL 24SSOP
• Manufacturer: International Rectifier

Specifications of IR22141SS

• Configuration: Half Bridge
• Input Type: Non-Inverting
• Delay Time: 440ns
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 1200V
• Voltage - Supply: 11.5 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Family Hvic: General Purpose HVICs
• Channels: 2
• Topology: Half Bridge
• Application: General Purpose / Motor Control
• Voffset: 1200
• Io+ (ma): 2000
• Io- (ma): 3000
• Separate Power And Logic Ground: Yes
• Uvlo: Vcc / Vbs
• Vbsuv+ / Vccuv+ Min (v): 9.3
• Vbsuv+ / Vccuv+ Typ (v): 10.2
• Vbsuv+ / Vccuv+ Max (v): 11.4
• Vbsuv- / Vccuv- Min (v): 8.7
• Vbsuv- / Vccuv- Typ (v): 9.3
• Vbsuv- / Vccuv- Max (v): 10.3
• Dt / Sdt Min (ns): 5700
• Dt / Sdt Typ (ns): 9250
• Dt / Sdt Max (ns): 13500
• T On Min (ns): 220
• T On Typ (ns): 440
• T On Max (ns): 660
• T Off Min (ns): 220
• T Off Typ (ns): 440
• T Off Max (ns): 660
• Fault Reporting: Yes
• Package: 24 Lead
• Part Status: Active & Preferred
• Special Features: Soft Shutdown and Desaturation Detection
• For Use With: IRMD2214SS - KIT DESIGN EVAL BOARD IR2214SSIRMD22141SS - KIT DESIGN EVAL BOARD/IR22141SS
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *IR22141SS

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where
R
R
R
(I
Characteristics”).
Table 1 reports the gate resistance size for two
commonly used IGBTs (calculation made using typical
datasheet values and assuming V
Output Voltage Slope: The turn-on gate resistor
R
(dV
linear behaviour, the maximum output slope can be
approximated by:
inserting the expression yielding I
As an example, table 2 shows the sizing of gate
resistance to get dV
popular IGBTs (typical datasheet values are used and
V
NOTICE : Turn on time must be lower than T
improper desaturation detection and SSD triggering.
2.6 Sizing the Turn-Off Gate Resistor
The worst case in sizing the turn-off resistor R
when the collector of the IGBT in the off state is forced
to commutate by an external event (e.g., the turn-on of
the companion IGBT). In this case the dV/dt of the
output node induces a parasitic current through C
R
O1+
CC
Gon
DRp
DRp
Gon
DRp
OUT
= 15 V is assumed).
= gate on-resistor
= driver equivalent on-resistance
is approximately given by
can be sized to control the output slope
=
/dt).
R
,I
O2+
TOT

 




Vcc
I
o
1
While the output voltage has a non-
=
+
and
R
t
t
R
Figure 21: R
SW
on
TOT
DRp
1
dV
R
+
DRp
dt
=
Vcc/Vb
+
Vcc
t
out
out
I
Vcc
on1
I
R
COM/Vs
o
o
C
/dt= 5 V/ns when using two
R
1
Gon
2
+
+
=
Vcc
Gon
RESoff
t
from
C
SW
Gon
I
RESoff
−
t
I
avg
avg
SW
⋅
−
Sizing
C
avg
V
CC
dV
RES
t
ge
on
dt
= 15 V).
and rearranging:
“Static
*
out
1
for
for
BL
Electrical
to avoid
t
t
SW
SW
Goff
RESoff
>
≤
is
t
t
on
on
19
1
1
flowing in R
drop at the gate exceeds the threshold voltage of the
IGBT, the device may self turn on, causing large
oscillation and relevant cross conduction.
The transfer function between the IGBT collector and
the IGBT gate then becomes:
which yields to a high pass filter with a pole at:
As a result, when τ is faster than the collector rise time
(to be verified after calculation) the transfer function can
be approximated by:
so that
in the time domain. Then the condition:
must be verified to avoid spurious turn on.
Rearranging the equation yields:
R
Figure 22: R
/ 1
V
V
V
V
V
V
DRn
th
ge
ge
de
ge
de
τ
ON
>
=
=
=
=
is approximately given by
V
(
1
s
(
R
ge
R
+
⋅
Goff
(
Goff
=
s
R
Goff
R
Goff
⋅
Goff
(
Off and High Side Turns On
R
R
+
Goff
(
s
+
IR21141/IR22141SSPbF
DRn
R
Goff
and R
⋅
Sizing: Current Path When Low Side is
R
Goff
R
(
+
DRn
R
<
R
DRn
HS Turning ON
R
+
Goff
Goff
C
+
DRn
)
R
DRn
)
⋅
RESoff
R
⋅
DRn
1
C
+
(
)
DRn
C
V
RESoff
(see Fig. 22). If the voltage
⋅
R
)
C
th
C
RESoff
DRn
⋅
C
)
⋅
RESoff
© 2009 International Rectifier
RESoff
C
IES
⋅
dV
dt
(
RESoff
)
⋅
C
⋅
dV
+
C
RESoff
dt
OFF
−
C
RESoff
de
R
dV
IES
DRn
dt
+
out
)
C
IES
dV/dt
)