IR22141SS International Rectifier, IR22141SS Datasheet - Page 14

• Manufacturer Part Number: IR22141SS
• Description: IC DRIVER HALF BRIDGE SGL 24SSOP
• Manufacturer: International Rectifier

Specifications of IR22141SS

• Configuration: Half Bridge
• Input Type: Non-Inverting
• Delay Time: 440ns
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 1200V
• Voltage - Supply: 11.5 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Family Hvic: General Purpose HVICs
• Channels: 2
• Topology: Half Bridge
• Application: General Purpose / Motor Control
• Voffset: 1200
• Io+ (ma): 2000
• Io- (ma): 3000
• Separate Power And Logic Ground: Yes
• Uvlo: Vcc / Vbs
• Vbsuv+ / Vccuv+ Min (v): 9.3
• Vbsuv+ / Vccuv+ Typ (v): 10.2
• Vbsuv+ / Vccuv+ Max (v): 11.4
• Vbsuv- / Vccuv- Min (v): 8.7
• Vbsuv- / Vccuv- Typ (v): 9.3
• Vbsuv- / Vccuv- Max (v): 10.3
• Dt / Sdt Min (ns): 5700
• Dt / Sdt Typ (ns): 9250
• Dt / Sdt Max (ns): 13500
• T On Min (ns): 220
• T On Typ (ns): 440
• T On Max (ns): 660
• T Off Min (ns): 220
• T Off Typ (ns): 440
• T Off Max (ns): 660
• Fault Reporting: Yes
• Package: 24 Lead
• Part Status: Active & Preferred
• Special Features: Soft Shutdown and Desaturation Detection
• For Use With: IRMD2214SS - KIT DESIGN EVAL BOARD IR2214SSIRMD22141SS - KIT DESIGN EVAL BOARD/IR22141SS
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *IR22141SS

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SY_FLT: The bi-directional SY_FLT pins communicate
each other through a local network. The logic signal is
active
desaturation activates the SY_FLT, which is then read
by the other gate drivers. When SY_FLT is active all the
drivers hold their output state regardless of the input
signals (H
state). This feature is particularly important in phase-to-
phase short circuit where two IGBTs are involved; in
fact, while one is softly shutting-down, the other must be
prevented from hard shutdown to avoid exiting SSD. In
the freeze state, the frozen drivers are not completely
inactive because desaturation detection still takes the
highest priority. SY_FLT communication has been
designed for creating a local network between the
drivers.
FAULT/SD:
communicate with each other and with the system
controller. The logic signal is active low. When low, the
FAULT/SD signal commands the outputs to go off by
hard shutdown. There are three events that can force
FAULT/SD low:
1.4.5 Fault Management at Start-up
When the bootstrap supply topology is used for
supplying the floating high side and the recommended
power supply start-up sequence is followed, FLT_CLR
pin must be kept active to prevent spurious diagnostic
signals being generated.
In the event of power inverter failure already present or
occurring during start-up (phase and/or rail supply short-
circuit, overload conditions induced by the load, etc.),
keeping the FLT_CLR pin active will also prevent the
real fault condition to be detected with the FAULT/SD
pin. In such a condition a large current increase in the
IGBT will desaturate the transistor, allowing the gate
FAULT
Figure 15: IR22141 used in a 3 phase application
1.
2.
3.
FAULT/SD
low.
SY_FLT
Desaturation detection event: the FAULT/SD
pin is latched low when SSD is over, and only a
FLT_CLR signal can reset it;
Undervoltage on V
forced low and held until the undervoltage is
active. This event is not latched;
FAULT/SD is externally driven low either from
the controller or from another IR21141/IR22141
device. This event is not latched; therefore the
FLT_CLR
FAULT/SD becomes high the device returns to
its normal operating mode.
IN
VCC
LIN
HIN
FLT_CLR
VSS
, L
phase U
IN
The
) they receive from the controller (freeze
The
HON
COM
HOP
SSH
DSH
LOP
LON
DSL
SSL
VB
VS
device
cannot
bi-directional
FAULT/SD
SY_FLT
VCC
LIN
HIN
FLT_CLR
VSS
CC
that
disable
phase V
: the FAULT/SD pin is
detects
HOP
HON
LON
COM
SSH
DSH
LOP
SSL
DSL
VB
VS
FAULT/SD
it.
FAULT/SD
SY_FLT
Only
VCC
LIN
HIN
FLT_CLR
VSS
the
phase W
when
IGBT
pins
COM
HOP
HON
SSH
DSH
LOP
LON
DSL
SSL
VB
VS
14
driver to detect and turn-off the desaturated transistor
with the integrated soft shutdown (SSD) protection.
As with a normal SSD sequence, during SSD the
SY_FLT output pin (active low, see Fig. 14) will report
the gate driver status. But now, being the FLT_CLR pin
already active, the gate driver will not generate a FAULT
signal by activating the FAULT/SD pin and it will not
enter hard shutdown.
To prevent the driver to resume charging the bootstrap
capacitor, therefore re-establishing the condition that will
determine again the occurrence of the large current
increase in the IGBT, it is recommended to monitor the
SY_FLT output pin. Should the SY_FLT output pin go
low during the start-up sequence, the controller must
interpret a power inverter failure is present, and stop the
start-up sequence.
1.5 Active Bias
For the purpose of sensing the power transistor
desaturation, the collector voltage is monitored (an
external high voltage diode is connected between the
IGBT’s collector and the IC’s DSH or DSL pin). The
diode is normally biased by an internal pull up resistor
connected to the local supply line (V
transistor is “on” the diode is conducting and the amount
of current flowing in the circuit is determined by the
internal pull up resistor value.
In the high side circuit, the desaturation biasing current
may become relevant for dimensioning the bootstrap
capacitor (see Fig. 19). In fact, a pull up resistor with a
low resistance may result in a high current that
significantly discharges the bootstrap capacitor. For that
reason, the internal pull up resistor typical value is of the
order of 100 k .
While the impedance of the DSH/DSL pins is very low
when the transistor is on (low impedance path through
the external diode down to the power transistor), the
impedance is only controlled by the pull up resistor when
the transistor is off. In that case, relevant dV/dt applied
by the power transistor during the commutation at the
output results in a considerable current injected through
the stray capacitance of the diode into the desaturation
detection pin (DSH/DSL). This coupled noise may be
easily reduced by using an active bias structure for the
sensing diode.
In IR21141/IR22141 the DSH/DSL pins integrate an
active pull-up structure respectively to V
down structure to V
The dedicated biasing circuit reduces the impedance on
the DSH/DSL pin when the voltage exceeds the V
threshold (see Fig. 16). This low impedance helps
rejecting the noise current injected by the parasitic
capacitance. When the power transistor is fully on, the
sensing diode is forward biased and the voltage at the
DSH/DSL pin decreases. At this point the biasing circuit
deactivates, to reduce the bias current of the diode as
shown in Fig. 16.
In certain switching conditions (short pulses, high
temperature) the recovery current of the external de-
saturation sensing diode might reach levels beyond the
capability of the active bias circuit. In order to avoid
malfunctions and damage for the IC an external Schottky
IR21141/IR22141SSPbF
S
/COM.
© 2009 International Rectifier
B
or V
B
/V
CC
CC,
). When the
and a pull-
DESAT