MCZ33937AEK Freescale Semiconductor, MCZ33937AEK Datasheet - Page 32

• Manufacturer Part Number: MCZ33937AEK
• Description: IC PRE-DRIVER 3PH ENH 54-SOIC
• Manufacturer: Freescale Semiconductor
• Series: SMARTMOS™r
• Type: 3 Phase Pre-Driverr

Specifications of MCZ33937AEK

• Configuration: 3 Phase Bridge
• Input Type: Non-Inverting
• Delay Time: 265ns
• Current - Peak: 600mA
• Number Of Configurations: 1
• Number Of Outputs: 3
• High Side Voltage - Max (bootstrap): 15V
• Voltage - Supply: 8 V ~ 40 V
• Operating Temperature: -40°C ~ 135°C
• Mounting Type: Surface Mount
• Package / Case: 54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RESET AND ENABLE
in
EN2), which together with the status of the VDD and VLS,
control the behavior of the IC.
following three modes:
The current consumption of the IC is at minimum.
Table 7. Functional Ratings
32
Table 6. Functions of RST, EN1 and EN2 Pins
33937
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Notes
Default State of input pin Px_LS, EN1, EN2, RST, SI, SCLK, if left open
(Driver output is switched off, high-impedance mode)
Default State of input pin Px_HS, CS if left open
(Driver output is switched off, high-impedance mode)
0
1
1
55.
RST
Table
The 33937 has three power modes of operation described
The operating status of the IC can be described by the
Sleep Mode - When RST is low, the IC is in Sleep mode.
• After entry to Enable Mode, the IC requires a pulse on
(
T
J
Px_LS in order to charge the bootstrap capacitor before
allowing the Px_HS to turn on. This pulse should be
long enough to guarantee the bootstrap capacitor is
charged (typically less than 50 µs), but the IC does not
= -40°C to 150°C and supply voltage range V
To assure a defined status for all inputs, these pins are internally biased by pull-up/down current sources.
6. There are three global control inputs (RST, EN1,
EN1, EN2
0x
x0
11
xx
Sleep Mode - in this mode (low quiescent current) the driver output stage is switched-off with a weak pull-down. All error
and SPI registers are cleared. The internal 5.0 V regulator is turned off and VDD is pulled low. All logic outputs except
SO are clamped to VSS.
Standby Mode - IC fully biased up and all functions are operating, the output drivers actively turn off all of the external
FETs (after initialization). The SPI port is functional. Logic level outputs are driven with low impedance. SO is high
impedance unless CS is low. V
Mode.
Enable Mode - (normal operation). Drivers are enabled; output stages follow the input command. After Enable, outputs
require a pulse on Px_LS before corresponding HS outputs will turn on in order to charge the bootstrap capacitor. All
error pin and register bits are active if detected.
FUNCTIONAL DEVICE OPERATION
(55)
SUP
DD
Characteristic
OPERATIONAL MODES
, Charge Pump and V
= V
PWR
Mode of Operation (Driver Condition)
= 5.0 to 45 V, C = 0.47 µF)
(55)
LS
• Standby Mode - The RST input is high while one of the
• Enable Mode - In order to enter the Enable mode
regulators are all operating. The IC is ready to move to Enable
Enable inputs is low. The IC is fully biased up and
operating, all the external FETs are actively turned off
by both High Side and Low Side gate drives. The IC is
ready to enter the Enable mode.
(normal mode of operation), and to operate the outputs,
the RST input must be high, and both Enable inputs
EN1 and EN2 must also be high.
enforce this condition. If there is an alternate means of
pre-charging the bootstrap capacitor, i.e. an external
resistor from Px_HS_S to GND, then a very brief pulse
of 100 ns is sufficient to reset the logic.
Analog Integrated Circuit Device Data
Freescale Semiconductor
High (>2.0 V)
Low (<1.0 V)
Value