ADP3419JRMZ-REEL ON Semiconductor, ADP3419JRMZ-REEL Datasheet - Page 7

• Manufacturer Part Number: ADP3419JRMZ-REEL
• Description: IC MOSFET DVR DUAL BOOTST 10MSOP
• Manufacturer: ON Semiconductor
• Type: High Side/Low Sider

Specifications of ADP3419JRMZ-REEL

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 32ns
• Current - Peak: 1A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 30V
• Voltage - Supply: 4.6 V ~ 6 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Number Of Drivers: 2
• Driver Configuration: Invert/Non-Invert
• Driver Type: High and Low Side
• Rise Time: 35ns
• Fall Time: 25ns
• Propagation Delay Time: 70ns
• Operating Supply Voltage (max): 6V
• Output Resistance: 1.7Ohm
• Operating Supply Voltage (min): 4.6V
• Operating Temp Range: 0C to 100C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 10
• Supply Voltage (min): 4.6 V
• Supply Current: 1.5 mA
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADP3419JRMZ-REEL; ADP3419JRMZ-REELTR

Theory of Operation
driving two N-channel MOSFETs in a synchronous buck
converter topology. A single PWM input signal is all that is
required to properly drive the high-side and the low-side
MOSFETs. Each driver is capable of driving a 3 nF load at
speeds up to 1 MHz. A more detailed description of the
ADP3419 and its features follows. Refer to the detailed
block diagram in Figure 16.
Undervoltage Lockout
MOSFET driver outputs low during VCC supply ramp-up.
The UVLO logic becomes active and in control of the driver
outputs at a supply voltage of no greater than 1.5 V. The
UVLO circuit waits until the VCC supply has reached a
voltage high enough to bias logic level MOSFETs fully on
before releasing control of the drivers to the control pins.
Driver Control Input
modulation signal of a switch-mode controller. IN can be
driven by 2.5 V to 5.0 V logic. The output MOSFETs are
driven so that the SW node follows the polarity of IN.
Low-Side Driver
ground-referenced low R
rectifier MOSFET. The bias to the low-side driver is
internally connected to the VCC supply and GND. Once the
supply voltage ramps up and exceeds the UVLO threshold,
the driver is enabled. When the driver is enabled, the driver’s
output is 180° out of phase with the IN pin. Table 2 shows
the relationship between DRVL and the different control
inputs of the ADP3419.
CROWBAR
DRVLSD
The ADP3419 is a dual MOSFET driver optimized for
The undervoltage lockout (UVLO) circuit holds both
The driver control input (IN) is connected to the duty ratio
The
Figure 16. Detailed Block Diagram of the ADP3419
SD
IN
4
1
2
3
low-side
VCC
AND BIAS
UVLO
5V
5
5
PROTECTION
OVERLAP
TIME−OUT
CIRCUIT
AND
driver
DS(ON)
is
designed
N-channel synchronous
D1
ADP3419
VCC
7
GND
to
10
6
9
8
BST
DRVH
SW
DRVL
drive
R
BST
http://onsemi.com
+
C
Q1
Q2
BST
V
DCIN
a
7
High-Side Driver
R
high-side driver is developed by an external bootstrap supply
circuit, which is connected between the BST and SW pins.
capacitor, C
pin is at ground, so the bootstrap capacitor charges up to
VCC through D1. Once the supply voltage ramps up and
exceeds the UVLO threshold, the driver is enabled. When IN
goes high, the high-side driver begins to turn on the
high-side MOSFET (Q1) by transferring charge from C
As Q1 turns on, the SW pin rises up to V
BST pin to V
gate-to-source voltage to hold Q1 on. To complete the cycle,
Q1 is switched off by pulling the gate down to the voltage at
the SW pin. When the low-side MOSFET (Q2) turns on, the
SW pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VCC again.
with the IN pin. Table 2 shows the relationship between
DRVH and the different control inputs of the ADP3419.
Overlap Protection Circuit
switches, Q1 and Q2, from being on at the same time. This
is done to prevent shoot-through currents from flowing
through both power switches and the associated losses that
can occur during their on-off transitions. The overlap
protection circuit accomplishes this by adaptively
controlling the delay from Q1’s turn-off to Q2’s turn-on, and
the delay from Q2’s turn-off to Q1’s turn-on.
turn-off and Q2’s turn-on, the overlap circuit monitors the
voltage at the SW pin and DRVH pin. When IN goes low, Q1
begins to turn off. The overlap protection circuit waits for
the voltage at the SW and DRVH pins to both fall below
1.6 V. Once both of these conditions are met, Q2 begins to
turn on. Using this method, the overlap protection circuit
ensures that Q1 is off before Q2 turns on, regardless of
variations in temperature, supply voltage, gate charge, and
drive current. There is, however, a timeout circuit that
overrides the waiting period for the SW and DRVH pins to
reach 1.6 V. After the timeout period has expired, DRVL is
asserted high regardless of the SW and DRVH voltages. In
the opposite case, when IN goes high, Q2 begins to turn off
after a propagation delay. The overlap protection circuit
waits for the voltage at DRVL to fall below 1.6 V, after which
DRVH is asserted high and Q1 turns on.
Low-Side Driver Shutdown
signal to shut down the synchronous rectifier. Under light
load conditions, DRVLSD should be pulled low before the
polarity reversal of the inductor current to maximize light
load conversion efficiency. DRVLSD can also be pulled low
for reverse voltage protection purposes.
DS(ON)
The high-side driver is designed to drive a floating low
The bootstrap circuit comprises a diode, D1, and bootstrap
When the driver is enabled, the driver’s output is in phase
The overlap protection circuit prevents both main power
To prevent the overlap of the gate drives during Q1’s
The low-side driver shutdown DRVLSD allows a control
N-channel MOSFET. The bias voltage for the
BST
. When the ADP3419 is starting up, the SW
DCIN
+ V
C(BST)
, which is enough
DCIN
, forcing the
BST
.