UBA2071AT/N1,118 NXP Semiconductors, UBA2071AT/N1,118 Datasheet - Page 15

• Manufacturer Part Number: UBA2071AT/N1,118
• Description: IC DVR HALF BRIDGE 24-SOIC
• Manufacturer: NXP Semiconductors
• Type: CCFL/EEFL Controllerr

Specifications of UBA2071AT/N1,118

• Package / Case: 24-SOIC (7.5mm Width)
• Frequency: 38 ~ 42kHz
• Current - Supply: 1.5mA
• Voltage - Supply: 14V
• Operating Temperature: -25°C ~ 100°C
• Driver Type: CCFL Drivers
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935285776118

NXP Semiconductors
UBA2071_A_1
Product data sheet
8.11 PWM dimming
Under normal operating conditions, the voltage across capacitor C2, which is connected
to the CVFB pin, will follow the voltage on the CIFB pin. During the lamps-on period of the
PWM dimming, the voltage across C3, which is connected to the CSWP pin, will follow the
voltage on the CVFB pin and therefore also the voltage on the CIFB pin.
The voltage on the CSWP pin is connected to the VCO input of the HF oscillator and thus
controls the switching frequency. If the load is assumed to be inductive an increase in the
frequency will cause a decrease in the lamp current, while a decrease in the frequency will
cause an increase in the lamp current.
The advantage of having a separate current regulation loop timing capacitor pin CIFB next
to the voltage regulation loop timing capacitor CVFB is that time constants for both loops
can be set independently. The separate PWM dimming sweep timing capacitor pin CSWP
makes it possible to set the PWM dimming sweep speed independent of the current and
voltage regulation loops.
Pulse Width Modulation (PWM) dimming is a method of reducing the average lamp light
output by switching the lamps on and off with a repetition rate or PWM frequency, f
high enough not to be seen by the human eye (but much lower than the inverter frequency
f
output can be varied over a wide range.
The voltage at the CSWP pin determines the actual switching frequency, it inverses in
proportion to the switching frequency. During the lamps-on period of the PWM dimming it
follows the voltage at the CVFB pin (the current I
between the CVFB pin and the CSWP pin).
Just prior to transitioning towards the lamps-off period of the PWM dimming the lamp
current control loop, see
CSWP pin is swept down, decaying the lamp current, leading in the PWM lamp-off
situation, after which the half bridge switch actions are stopped, resulting in true zero lamp
current. see
sw
Fig 11. Lamp frequency control circuit
). By varying the lamp-on to lamp-off, period ratio, called the duty cycle
to CCFLs
R1
IFB
Figure
UBA2071
DSR
V ref(creg)
9. In the meantime the regulation level is preserved in C1 and C2. The
Rev. 01 — 23 June 2008
Figure
OTA
11, is opened by opening switches S1. The voltage on the
S1
CIFB
C1
Half bridge control IC for CCFL backlighting
UBA2071; UBA2071A
ch(CSWP)
CVFB
C2
I ch(CVFB)
is drained by the tracking circuit
I ch(CSWP)
PWMD
0
1
S2
CSWP
© NXP B.V. 2008. All rights reserved.
I dch(CSWP)
C3
PWM
to VCO
014aaa106
, the light
PWM
15 of 35
,