UBA2071AT/N1,118 NXP Semiconductors, UBA2071AT/N1,118 Datasheet
UBA2071AT/N1,118
Specifications of UBA2071AT/N1,118
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UBA2071AT/N1,118 Summary of contents
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UBA2071; UBA2071A Half bridge control IC for CCFL backlighting Rev. 01 — 23 June 2008 1. General description The UBA2071 and UBA2071A are high voltage ICs intended to drive Cold Cathode Fluorescent Lamps (CCFLs) or External Electrode Fluorescent Lamps (EEFLs) ...
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... NXP Semiconductors I Bidirectional pin acting both as fault signaling output and input, allowing external fault interfacing to operate via the integrated fault timer. I Brightness level adjustment through PWM dimming. I Integrated PWM generator. I Power-down mode. I Communication pin for master / slave operation blocking capacitor pre-charging sequence. ...
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... NXP Semiconductors Table amb otherwise specified. All voltages are measured with respect to signal ground (SGND, pin 10). SGND and PGND connected together. Currents are positive when flowing into the IC. Symbol V th(ov)(VFB) t to(fault) I source(drv) R sink(drv) f PWM PWMD [1] Given frequency is switching frequency of GL and GH. Sawtooth frequency on CF pin is twice as high. ...
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... NXP Semiconductors 6. Block diagram INTERNAL IREF SUPPLY VDD AND REFERENCE SGND CIRCUITS OSCILLATOR CSWP TRACK AND CVFB SWEEP OVER- VFB VOLTAGE SENSING ARCING DETECTION OVER- CURRENT DETECTION DOUBLE LAMP IFB SIDE CURRENT RECTIFIER SENSING Fig 1. Block diagram UBA2071_A_1 Product data sheet ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. 7.2 Pin description Table 3. Pin description Symbol Pin Description IFB 1 current feedback input. CIFB 2 current regulation capacitor. VFB 3 voltage feedback input CVFB 4 voltage regulation capacitor CSWP 5 frequency sweep capacitor CT 6 fault timing capacitor CF 7 HF-oscillator timing ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Description NONFAULT 12 status signal input/output PWMD 13 digital PWM dimming input/output PWMA 14 analog PWM dimming input EN 15 chip enable input VDD 16 supply input PGND 17 power ground GL 18 low-side driver output n.c. 19 not connected n.c. ...
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... NXP Semiconductors Fig 3. 8.1 Supply, Start-up and UnderVoltage LockOut (UVLO) Fig 4. The UBA2071 is supplied via the VDD pin as shown in either made by the inverter itself, using auxiliary fixed supply voltage. A start-up current source that can supply minimal resistor to the half bridge supply voltage. ...
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... NXP Semiconductors 8.2 V clamp DD When the UBA2071 is disabled (EN pin low the stop state, the V activated. The V prevents the start-up current source from charging the V voltage. The maximum current that is allowed to be delivered by the start-up current source is determined by the clamp voltage as stated in ...
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... NXP Semiconductors Fig 5. 8.5 Non-overlap During each transition between the two states GL high/GH low and GL low/GH high, GL and GH will both be low for a fixed time charged or discharged by the load current (presuming the load always has an inductive behavior), and thus enabling zero voltage switching, see 8 ...
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... NXP Semiconductors When the voltage on the EN pin goes over V pin below V the voltage on the EN pin goes over V V th(L)(EN) mode. When the voltage on the EN pin goes over V initial ignition frequency sweep and normal operation mode. shows three examples of how the enable input can be used: Fig 6. 1. Digital enable input with DC blocking capacitor charging. R1 and C1 defi ...
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... NXP Semiconductors (H)2(EN) EN (H)1(EN) (L)(EN Fig 7. Remark: Due to the nature of the charging sequence, V charged to 0.5 charging mode longer than necessary, V constant made by R1 and C1 in example cannot become more than 0.5 Cblock V than 0.5 Cblock the IC may get stuck in DC blocking capacitor charging mode. ...
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... NXP Semiconductors (1) Indicates lamp-OFF. (2) Indicates lamp-ON. Fig 8. Advantage of the sweep rather than a fixed ignition frequency is that sensitivity for spread in resonance frequency is much lower. Once the lamps are ignited the frequency sweep-down continues, gradually increasing the lamp current (the resonance circuit should now still be inductive, so current increases as ...
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... NXP Semiconductors Fig 9. The lamps start switching again on period GL and GH and the frequency is swept back to the regulation frequency f proportional to the capacitor connected to the CSWP pin. 8.9 Overvoltage control The overvoltage control circuit is intended to prevent the transformer output voltage from exceeding its maximum rating. It can also be used to regulate the output voltage to the required lamp ignition voltage ...
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... NXP Semiconductors When the voltage on the VFB pin exceeds V handling of fault conditions, see changed to the discharge current I and the output voltage of the transformer will decrease VFB pin drops below V voltage of the transformer will increase again. Because the charging and discharging of the CVFB capacitor follows the ripple on the VFB pin voltage, the feedback gain of the voltage control loop is set by the ripple on the feedback signal ...
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... NXP Semiconductors to CCFLs Fig 11. Lamp frequency control circuit Under normal operating conditions, the voltage across capacitor C2, which is connected to the CVFB pin, will follow the voltage on the CIFB pin. During the lamps-on period of the PWM dimming, the voltage across C3, which is connected to the CSWP pin, will follow the voltage on the CVFB pin and therefore also the voltage on the CIFB pin ...
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... NXP Semiconductors PWM lamp-on situation is reached again through a reverse sequence of events, starting the half bridge actions, increasing the voltage on CSWP, increasing the lamp current back to the controlled value. Switch S1 is closed (conducting) again when the voltage on the CSWP pin has reached the voltage on the CVFB pin again. ...
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... NXP Semiconductors Fig 13. PWM dimming configurations When the CPWM pin is connected to ground the IC is put in digital or slave mode and the PWMD pin is an input. The internal PWM generator is not used. The IC uses the PWM signal provided on the PWMD pin. PWM dimming of multiple ICs can be synchronized by configuring one IC as master and the others as slaves and connecting all PWMD pins together ...
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... NXP Semiconductors Fig 14. Fault timer waveforms If the fault timer is inactive, the CT pin voltage is 1 Vbe, about 0.7 V. The CT timer has a protection that prevents the IC to start up if the CT pin is shorted to GND. 8.13 Communication The UBA2071 and UBA2071A have a dedicated communication pin, the COMM pin, for communicating with a slave half bridge driver (like the UBA2073), for instance for use in a balanced half bridge driver confi ...
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... NXP Semiconductors • OverCurrent Protection (OCP), • bad contact or ARCing (ARC), • Ignition Failure (IF), • open or shorted current feedback (IFB pin open/short), • open or shorted voltage feedback (VFB pin open/short) • Hard Switching (HS). There are also two pins, the NONFAULT pin and the COMM pin, via which a fault can be signalled to the IC external circuit ...
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... NXP Semiconductors 8.14.2 Overvoltage protection The overvoltage control, see voltage from exceeding its maximum rating. The overvoltage control level has least at the required lamp ignition voltage, otherwise the lamps may not ignite. Once the lamps are on and in steady state, the transformer output voltage will usually be about half the required ignition voltage for CCFLs ...
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... NXP Semiconductors times in case overvoltage and overvoltage extra are detected at the same moment (curve (1)) and if overvoltage, overvoltage extra and hard switching are detected at the same moment (curve (2)). The first parts of the curves are dashed because an internal filter makes that VFB needs to be above V overvoltage extra to react at all ...
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... NXP Semiconductors duration longer than t the control circuits that arcing has been detected. When arcing is detected, PWM dimming is disabled and the fault timer is started. 8.14.8 Ignition Failure (IF) When the current control loop comes close to its regulation point, the lamps are assumed (ignited) ...
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... NXP Semiconductors The signal from the voltage signal and the signal to the current signal. In this way a driving conflict is prevented. Also, it leaves the possibility for the outside world to see the signal from the IC even while a fault condition is being signalled to the IC in the meantime, as illustrated in Fig 18 ...
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... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are measured with respect to signal ground (SGND pin 10). Symbol Parameter V voltage on pin NONFAULT NONFAULT V voltage on pin VFB VFB V voltage on pin IFB IFB ESD V electrostatic discharge voltage human body model: ESD 10 ...
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... NXP Semiconductors Table 6. Characteristics …continued amb VDD IREF voltages are measured with respect to signal ground (SGND, pin 10). SGND and PGND connected together. GL, GH, COMM, NONFAULT and PWMD pins left open (unless otherwise specified). Currents are positive when flowing into the IC. ...
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... NXP Semiconductors Table 6. Characteristics …continued amb VDD IREF voltages are measured with respect to signal ground (SGND, pin 10). SGND and PGND connected together. GL, GH, COMM, NONFAULT and PWMD pins left open (unless otherwise specified). Currents are positive when flowing into the IC. ...
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... NXP Semiconductors Table 6. Characteristics …continued amb VDD IREF voltages are measured with respect to signal ground (SGND, pin 10). SGND and PGND connected together. GL, GH, COMM, NONFAULT and PWMD pins left open (unless otherwise specified). Currents are positive when flowing into the IC. ...
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... NXP Semiconductors 12. Application information Figure 19 from a high voltage DC source and the IC is supplied by means supply (C14, C15, Z1 and D1). Two lamps are connected, each to the output of its own transformer. The leakage inductance of this transformer provides the ballast impedance for the lamps. An analog voltage is converted to a PWM signal to provide for the desired brightness level. ...
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R2 HVDC NONFAULT C2 VDD GND CN1 PWMA CIFB C4 PWMD CVFB CSWP R1 IREF SGND C8 CPWM PWMA PWMD COMM (1) Optional lamp short protection is available via the NONFAULT pin. ...
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HVsupply UBA2071 VDD IREF CF CT CSWP CVFB CIFB CPWM SGND PWMA PWMA enable EN PWMD PWMD Fig 20. Example of balanced backlighting application PGND IFB VFB COMM NONFAULT UBA2073 GH VDD COMM ...
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... NXP Semiconductors 13. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 22. Package outline SOT340 (SSOP24) ...
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... NXP Semiconductors 14. Revision history Table 7. Revision history Document ID Release date UBA2071_A_1 20080623 UBA2071_A_1 Product data sheet Half bridge control IC for CCFL backlighting Data sheet status Change notice Product data sheet - Rev. 01 — 23 June 2008 UBA2071; UBA2071A Order number Supersedes - - © NXP B.V. 2008. All rights reserved. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 6 8.1 Supply, Start-up and UnderVoltage LockOut (UVLO 8.2 V clamp 8.3 Enable ...