A6285EET-T Allegro Microsystems Inc, A6285EET-T Datasheet - Page 12

IC LED DRIVER LINEAR 32-QFN

A6285EET-T

Manufacturer Part Number
A6285EET-T
Description
IC LED DRIVER LINEAR 32-QFN
Manufacturer
Allegro Microsystems Inc
Type
Linear (Non-Switching)r
Datasheet

Specifications of A6285EET-T

Operating Temperature
-40°C ~ 85°C
Topology
PWM
Constant Current
Yes
Number Of Outputs
16
Internal Driver
Yes
Type - Primary
Backlight
Type - Secondary
Color, White LED
Frequency
30MHz
Voltage - Supply
3 V ~ 5.5 V
Voltage - Output
12V
Mounting Type
Surface Mount
Package / Case
32-VFQFN Exposed Pad
Current - Output / Channel
80mA
Internal Switch(s)
Yes
Led Driver Application
Display
No. Of Outputs
16
Output Current
80mA
Output Voltage
12V
Input Voltage
3V To 5.5V
Dimming Control Type
PWM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Efficiency
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
620-1224-5
A6285
Load Supply Voltage (V
These devices are designed to operate with driver voltage drops
(V
V
driver, package power dissipation will increase significantly. To
minimize package power dissipation, it is recommended to use
the lowest possible load supply voltage, V
voltage dropping, V
with V
(V
per diode) for a group of drivers (see figure 3). If the available
voltage source will cause unacceptable power dissipation and
series resistors or diodes are undesirable, a voltage regulator can
be used to provide V
For reference, typical LED forward voltages are:
F
DS
Z
, of 1.2 to 4.0 V. If higher voltages are dropped across the
), or for a series string of silicon diodes (approximately 0.7 V
) of 1.0 to 3.0V, with one or more LED forward voltages,
DROP
Figure 12. Typical application voltage drops
= I
O
× R
LED Type
V
Infrared
DROP
DROP
Yellow
Amber
White
Green
LED
Blue
DROP
Red
.
, according to the following formula:
LED
for a single driver or for a Zener diode
= V
)
LED
– V
F
1.9 to 2.65
1.6 to 2.25
3.5 to 4.0
3.0 to 4.0
1.8 to 2.2
2.0 to 2.1
1.2 to 1.5
16-Channel Constant-Current Latched LED Driver
– V
V
F
LED
(V)
DS ,
, or to set any series
with Open LED Detection and Dot Correction
Application Information
Pattern Layout
The logic and power grounds should be kept separate, terminated
at one location. The exposed metal pad must be connected to a
large power ground plane, allowing the copper to dissipate heat.
Where multiple devices are cascaded, multilayer boards are
recommended.
REXT should be placed as close as possible to the device, keep-
ing a short distance between the REXT pin and ground.
Decoupling capacitors should be used liberally. 0.1 μF should
be placed on the logic supply pin, and 10 μF placed between
the common VLED line and the device ground at least at every
second device.
Package Power Dissipation (P
The maximum allowable package power dissipation based on
package type is determined by:
where R
the circuit board, determined experimentally. Power dissipation
levels based on the package are shown in the Package Thermal
Characteristics section (see page 7).
The actual package power dissipation is determined by:
where DC is the duty cycle. The value 16 represents the maxi-
mum number of available device outputs.
When the load supply voltage, V
P
used (see figure 12).
Reducing the percent duty cycle, DC, will also reduce power dis-
sipation.
D(act)
> P
θJA
D(max)
P
is the thermal resistance of the package mounted on
D(act)
, an external voltage reducer (V
= DC × (V
P
D(max)
= (150 – T
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
DS
× I
D
LED
)
O
× 16) + (V
, is greater than 3 to 5 V, and
A
) / R
θJA
DD
,
DROP
× I
DD
) must be
) ,
12

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