ISL97635IRZ-T Intersil, ISL97635IRZ-T Datasheet - Page 20

• Manufacturer Part Number: ISL97635IRZ-T
• Description: IC LED DRVR WHT/RGB BCKLGT 24QFN
• Manufacturer: Intersil
• Type: Backlight, White LED, RGBr

Specifications of ISL97635IRZ-T

• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 8
• Internal Driver: Yes
• Type - Primary: Automotive, Backlight
• Type - Secondary: RGB, White LED
• Frequency: 600kHz, 1.2MHz
• Voltage - Supply: 6 V ~ 24 V
• Voltage - Output: 34.5V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 35mA
• Internal Switch(s): Yes
• Efficiency: 91%
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The PWM_SEL bit determines whether the SMBus or PWMI
input should drive the output brightness in terms of PWM
dimming. When PWM_SEL bit is 1, the PWMI drives the
output brightness regardless of what the PWM_MD is.
When the PWM_SEL bit is 0, the PWM_MD bit selects the
manner in which the PWM dimming is to be interpreted;
when this bit is 1, the PWM dimming is based on the SMBus
brightness setting. When this bit is 0, the PWM dimming
reflects a percentage change in the current brightness
programmed in the SMBus Register 0x00, i.e. DPST
(Display Power Saving Technology) mode, as shown in
Equation 15:
Where:
Cbt = Current brightness setting from SMBus Register 0x00
without influence from the PWMI
DPST Brightness
PWM_MD PWM_SEL
RESERVED RESERVED RESERVED RESERVED RESERVED
Bit 7 (R/W)
Bit 7 (R/W)
TABLE 3. OPERATING MODES SELECTED BY DEVICE
REGISTER 0x00
REGISTER 0x01
BRT7
X
1
0
BIT ASSIGNMENT
BIT ASSIGNMENT
PWM_SEL
PWM_MD
BRT[7..0]
BL_CTL
CONTROL REGISTER BITS 1 AND 2
Bit 6 (R/W)
Bit 6 (R/W)
1
0
0
BRT6
=
Cbt
PWMI Mode
SMBus Mode
SMBus and PWMI Mode with DPST
PWM BRIGHTNESS CONTROL REGISTER
×
PWMI
DEVICE CONTROL REGISTER
Bit 5 (R/W)
Bit 5 (R/W)
20
= 256 steps of PWM brightness levels
= PWM mode select bit (1 = absolute brightness,
0 = % change) default = 0
= Brightness control select bit (1 = control by
PWMI, 0 = control by SMBus) default = 0
= BL On/Off (1 = On, 0 = Off) default = 0
BRT5
FIGURE 23. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER
FIGURE 24. DESCRIPTIONS OF DEVICE CONTROL REGISTER
MODE
Bit 4 (R/W)
BIT FIELD DEFINITIONS
Bit 4 (R/W)
BIT FIELD DEFINITIONS
BRT4
(EQ. 15)
Bit 3 (R/W)
Bit 3 (R/W)
BRT3
ISL97635
Bit 2 (R/W)
Bit 2 (R/W)
PWM_MD
BRT2
PWMI = is the percent duty cycle of the PWMI
For example, the Cbt = 50% duty cycle programmed in the
SMBus Register 0x00 and the PWM frequency is tuned to be
200Hz with an appropriate capacitor at the FPWM pin. On the
other hand, PWMI is fed with a 1kHz 30% high PWM signal.
When PWM_SEL = 0 and PWM_MD = 0, the device is in DPST
operation where DPST brightness = 15% PWM dimming at
200Hz.
• All reserved bits return a “0” when read.
• All reserved bits have no functional effect when written.
• All defined control bits return their current, latched value
• A value of 1 written to BL_CTL turns on the BL in 4ms or less
• A value of 0 written to BL_CTL immediately turns off the BL.
• **Note that the behavior of Register 0x00 (Brightness
when read.
after the write cycle completes. The BL is deemed to be on
when Bit 3 BL_STAT of Register 0x02 is 1 and Register
0x09 is not 0. See Figures 23 and 24.
The BL is deemed to be off when Bit 3 BL_STAT of Register
0x02 is 0 and Register 0x09 is 0. See Figures 23 and 24.
Control Register) is affected by certain combinations of the
control bits, as shown in Table 3 “Operating Modes
Selected by Device Control Register Bits 1 and 2.”
Bit 1 (R/W)
PWM_SEL
Bit 1 (R/W)
BRT1
Bit 0 (R/W)
Bit 0 (R/W)
BL_CTL
BRT0
December 22, 2008
FN6434.2