ISL97674IRZ Intersil, ISL97674IRZ Datasheet

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ISL97674IRZ

Manufacturer Part Number
ISL97674IRZ
Description
IC LED DVR PWM CTRL 6CH 20QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL97674IRZ

Topology
PWM, Step-Up (Boost)
Number Of Outputs
6
Internal Driver
Yes
Type - Primary
Automotive, Backlight
Type - Secondary
RGB, White LED
Frequency
600kHz, 1.2MHz
Voltage - Supply
4.5 V ~ 26.5 V
Voltage - Output
*
Mounting Type
Surface Mount
Package / Case
20-VFQFN Exposed Pad
Operating Temperature
-40°C ~ 85°C
Current - Output / Channel
40mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
6-Channel LED Driver with Phase Shift Control and
Frame Rate to Dimming Frequency
Synchronization
ISL97674
The ISL97674 is a 6-Channel 45V dual dimming capable
LED driver that can be used with either SMBus/I
PWM signal for dimming control. The ISL97674 drives 6
channels of LED to support 78 LEDs from 4.5V to 26V or
48 LEDs from a boost supply of 2.7V to 26V and a
separate 5V bias on the ISL97674 VIN pin.
The ISL97674 compensates for non-uniformity of the
forward voltage drops in the LED strings with its 6 voltage
controlled-current source channels. Its headroom control
monitors the highest LED forward voltage string for output
regulation, to minimize the voltage headroom and power
loss in a typical multi string operation.
The ISL97674 features optional channel phase shift
control to minimize the input, output ripple
characteristics and load transients as well as spreading
the light output to help reduce the video and audio
interference from the backlight driver operation. The
phase shift can be programmed with equal phase angle
or adjustable in 7-bit resolution. In addition, the
ISL97674 also has a unique V
30Hz ~ 120Hz frame signal and synchronizes it to the
dimming frequency to minimize panel to panel visual
interference variation. The dimming frequencies are
available from 200Hz to 30kHz and can be synchronized
from 140Hz to 1085Hz.
Typical Application Circuit
June 25, 2010
FN7634.0
V
1
IN
= 4.5~26.5V
SYNC
FIGURE 1. ISL97674 TYPICAL APPLICATION DIAGRAM
function that accepts
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
17
1
4
18
8
2
7
6
3
5
2
FAULT
VIN
VDC
COMP
SCL
SDA
EN/PWM
VSYNC
PLLC
RSET
C or
ISL97674
PGND
AGND
OVP
CH0
CH1
CH2
CH3
CH4
CH5
LX
Features
• 6 Channels
• Frame Rate to Dimming Frequency Synchronization
• 4.5V to 26.5V Input
• 45V Output Max
• Up to 40mA LED Current per channel
• Extensive Dimming Control
• Optional Master Fault Protection
• PWM Dimming Linearity 0.4%~100% <30kHz
• 600kHz/1.2MHz selectable switching frequency
• Dynamic Headroom Control
• Protections with Flag Indication
• Current Matching ±0.7%
• 20 Ld 4mmx3mm QFN Package
Applications
• Notebook Displays WLED or RGB LED Backlighting
• LCD Monitor LED Backlighting
• Automotive Displays LED Backlighting
16
19
10
11
12
13
14
15
20
9
- PWM/DPST Dimming, I
- String Open/Short Circuit, V
- Optional Master Fault Protection
All other trademarks mentioned are the property of their respective owners.
shift, and 0.007% Direct PWM dimming at 200Hz
Overvoltage and Over-Temperature Protections
|
V
Intersil (and design) is a registered trademark of Intersil Americas Inc.
OUT
= 45V*, 40mA PER STRING
*V
IN
Copyright Intersil Americas Inc. 2010. All Rights Reserved
> 12V
2
C 8-bit with equal phase
OUT
Short Circuit,

Related parts for ISL97674IRZ

ISL97674IRZ Summary of contents

Page 1

... AGND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners 8-bit with equal phase Short Circuit, OUT > 12V IN Copyright Intersil Americas Inc ...

Page 2

Block Diagram VIN = 4.5V~26.5V VIN REG REG VDC Bias fsw OSC & RAMP Comp GM COMP AMP REF + - RSET GEN REF_OVP GND REF_VSC EN/PWM PWM Ctrl Ckt VSYNC PLL PLLC SCL I2C SDA Control 2 ISL97674 10uH/3A ...

Page 3

... Ordering Information PART NUMBER PART PACKAGE (Notes MARKING (Pb-free) ISL97674IRZ 7674 20 Ld 4x3 QFN L20.3x4 NOTES: 1. Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die ...

Page 4

Table of Contents Typical Application Circuit ................................. 1 Block Diagram ................................................... 2 Pin Descriptions (I = Input Output Supply)..................................................... 3 Absolute Maximum Ratings . . . . . . . . . . . . . ...

Page 5

... Thermal Resistance (Typical QFN Package (Notes 4, 5, 7). Thermal Characterization (Typical QFN Package (Note Maximum Continuous Junction Temperature . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = +25° CONDITION ≤13 LEDs per channel (3.2V/20mA type) 4.5V < V ≤ ...

Page 6

Electrical Specifications All specifications below are tested at T unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER DESCRIPTION BOOST SWILimit Boost FET Current Limit r Internal Boost Switch ON-resistance DS(ON) SS Soft-start ...

Page 7

Electrical Specifications All specifications below are tested at T unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER DESCRIPTION V Fault Clamp Voltage with Respect to FAULT V IN LXStart_thres Lx Start-up Threshold ...

Page 8

Typical Performance Curves 100 24V 12V LED(mA) FIGURE 3. EFFICIENCY 20mA LED CURRENT (100% LED DUTY CYCLE 100 90 ...

Page 9

Typical Performance Curves 1.2 1.0 0.8 0 0.4 0 FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING DUTY CYCLE vs V FIGURE 11. V RIPPLE VOLTAGE, V OUT AT 20mA/CHANNEL FIGURE ...

Page 10

Typical Performance Curves FIGURE 15. LINE REGULATION WITH V FROM 26V TO 6V FOR 6P12S AT 20mA/CHANNEL FIGURE 17. LOAD REGULATION WITH I FROM 100 PWM DIMMING 12V, 6P12S AT 20mA/CHANNEL IN Theory of Operation PWM ...

Page 11

REF REF - RSET RSET PWM DIMMING DC DIMMING FIGURE 19. SIMPLIFIED CURRENT SOURCE CIRCUIT The LED peak current is set by translating the R current to the output with a scaling factor of 401.8/R ...

Page 12

Method 2 (External applied PWM) To use this mode users need to set Register 0x01 to 0x03 The average LED current of each channel can also be controlled by an external PWM signal as: × I PWM = ( ) ...

Page 13

V Frame Rate to Dimming SYNC Synchronization The ISL97674 features a V function that allows the SYNC frame rate synchronized with the PWM dimming frequency that minimizes the potential interference generated by the mismatch between frame rate to PWM dimming ...

Page 14

LED stacks to fault out. See Table 1 for more details. A fault condition that results in high input current due to a short ...

Page 15

VIN FAULT DRIVER IMAX ILIMIT VSET/2 REG FAULT/ STATUS REGISTER CASE FAILURE MODE DETECTION MODE 1 CH0 Short Circuit Upper Over-Temperature Protection limit (OTP) not triggered and CH0 < CH0 Short Circuit Upper OTP triggered but VCH0 < ...

Page 16

CASE FAILURE MODE DETECTION MODE 7 CH0 LED Open Upper OTP not Circuit but has triggered but CHx > 4V paralleled Zener 8 Channel-to- Lower OTP triggered Channel but CHx < 4V ΔVF too high 9 Channel-to- Upper OTP triggered ...

Page 17

S Slave Address W A Master to Slave Slave to Master Write Byte The Write Byte protocol is only three bytes long. The first byte starts with the slave address followed by the “command code,” which ...

Page 18

ADDRESS REGISTER BIT 7 BIT 6 0x08 Configuration DsblPLL DirectPWM PWMtoDC BstSlew Register 0x09 Output Channel Reserved Reserved Register 0x0A Phase Shift Deg Equal Phase Phase Shift6 0x0B PLLC PLLDivBy4 Divide6 ADDRESS REGISTER 0x00 PWM Brightness Control Register 0x01 Device ...

Page 19

PWM Brightness Control Register (0x00) The Brightness control resolution has 256 steps of PWM duty cycle adjustment. The bit assignment is shown in Figure 30. All of the bits in this Brightness Control Register can be read or write. Step ...

Page 20

Device Control Register (0x01) • This register has two bits that control either 2 SMBus/I C controlled or external PWM controlled PWM dimming and a single bit that controls the BL ON/OFF state. The remaining bits are reserved. The bit ...

Page 21

... BIT FIELD DEFINITIONS = Manufacturer ID. See “Si Revision MFG[3..0] Register (0x03)” on page 20. data decimal correspond to other vendors data 9 in decimal represents Intersil ID data decimal are reserved data 15 in decimal Manufacturer ID is not implemented REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins) ...

Page 22

DC BRIGHTNESS CONTROL REGISTER 0x07 REGISTER BRTDC7 BRTDC6 BRTDC5 Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT = 256 steps of DC ...

Page 23

REGISTER 0x08 CONFIGURATION REGISTER DsblPLL DirectPWM PWMtoDC Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) BIT ASSIGNMENT When 1, PLL is disabled and PWM frequency is set by resistor to ground on PLLC pin. DsblPLL Forces the PWMI signal ...

Page 24

REGISTER 0x0B PLL CONTROL REGISTER PLLDivBy4 PLLDivide6 PLLDivide5 PLLDivide4 PLLDivide3 PLLDivide2 PLLDivide1 PLLDivide0 Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) BIT ASSIGNMENT PLLDivBy4 PLLDivide[6..0] If PLLDivBy4 = 0, Freq(PWM) = Freq(Vsync PLLDivide)/5 If PLLDivBy4 = ...

Page 25

Inductor The selection of the inductor should be based on its maximum current (I ) characteristics, power SAT dissipation (DCR), EMI susceptibility (shielded vs unshielded), and size. ...

Page 26

Schottky Diode A high speed rectifier diode is necessary to prevent excessive voltage overshoot, especially in the boost configuration. Low forward voltage and reverse leakage current will minimize losses, making Schottky diodes the preferred choice. Although the Schottky diode turns ...

Page 27

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries ...

Page 28

Package Outline Drawing L20.3x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/10 3. PIN 1 INDEX AREA A TOP VIEW (2.65) (3.80) (1.65) (2.80) TYPICAL RECOMMENDED LAND PATTERN 28 ISL97674 A B 20X 4 4.00 0.15 ...

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