ISL97671IRZ-T Intersil, ISL97671IRZ-T Datasheet - Page 20

• Manufacturer Part Number: ISL97671IRZ-T
• Description: IC LED DVR PWM CTRL 6CH 20QFN
• Manufacturer: Intersil

Specifications of ISL97671IRZ-T

• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 6
• Internal Driver: Yes
• Type - Primary: Automotive, Backlight
• Type - Secondary: RGB, White LED
• Frequency: 600kHz ~ 1.2MHz
• Voltage - Supply: 4.5 V ~ 26.5 V
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 40mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

PWM Brightness Control Register (0x00)
The Brightness control resolution has 256 steps of PWM
duty cycle adjustment. The bit assignment is shown in
Figure 30. All of the bits in this Brightness Control
Register can be read or write. Step 0 corresponds to the
minimum step where the current is less than 10µA.
Steps 1 to 255 represent the linear steps between 0.39%
and 100% duty cycle with approximately 0.39% duty
cycle adjustment per step.
• An SMBus/I
ADDRESS
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
the PWM brightness level only if the backlight
controller is in SMBus/I
REGISTER 0x00
0x07
0x08
0x09
0x0A
BRT7
BIT ASSIGNMENT
BRT[7..0]
DC Brightness Control
Register
Output Channel Mask/Fault
Readout Register
Phase Shift Degree
Configuration Register
2
C Write Byte cycle to Register 0x00 sets
BRT6
REGISTER
PWM BRIGHTNESS CONTROL
FIGURE 30. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER
20
2
BRT5
= 256 steps of PWM brightness levels
C mode (see Table 3)
TABLE 2B. DATA BIT DESCRIPTIONS (Continued)
REGISTER
BIT FIELD DEFINITIONS
BRTDC[7..0] = 256 steps of DC brightness control
DirectPWM = Forces the PWM input signal to directly control the current sources.
Bits 3, 4, and 5 should be 1, 1, 0
FSW = Switching frequencies selection, FSW = 0 = 1.2MHz. FSW = 1 = 600kMHz
VSC[1..0] = Short circuit thresholds selection, 0 = disabled, 1 = 3.6V, 2 = 4.8V, 3 =
5.85V
CH[5..0] = Output Channel Read and Write. In Write, 1 = Channel Enabled, 0 =
Channel Disabled. In Read, 1 = Channel OK, 0 = Channel Not OK/Channel disabled
EqualPhase = Controls phase shift mode - When 1, phase shift is 360/N (where N is
the number of channels enabled). When 0, phase shift is defined by PhaseShift<6:0>.
PS[6..0] = 7-bit Phase shift setting - phase shift between each channel is
PhaseShift<6:0>/(255*PWMFreq). In direct PWM modes, phase shift between each
channel is PhaseShift<6:0>/12.8MHz.
BRT4
BRT3
ISL97671
• An SMBus/I
• An SMBus/I
• An SMBus/I
• Default value for Register 0x00 is 0xFF.
BRT2
Operating Modes selected by Device Control Register
Bits 1 and 2).
returns the programmed PWM brightness level.
the backlight controller to the maximum brightness.
the backlight controller to the minimum brightness
output.
DATA BIT DESCRIPTIONS
BRT1
2
2
2
C Read Byte cycle to Register 0x00
C setting of 0xFF for Register 0x00 sets
C setting of 0x00 for Register 0x00 sets
BRT0
June 24, 2010
FN7631.0