ISL97671IRZ-T Intersil, ISL97671IRZ-T Datasheet - Page 18

• Manufacturer Part Number: ISL97671IRZ-T
• Description: IC LED DVR PWM CTRL 6CH 20QFN
• Manufacturer: Intersil

Specifications of ISL97671IRZ-T

• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 6
• Internal Driver: Yes
• Type - Primary: Automotive, Backlight
• Type - Secondary: RGB, White LED
• Frequency: 600kHz ~ 1.2MHz
• Voltage - Supply: 4.5 V ~ 26.5 V
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 40mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

SMBus/I
The ISL97671 can be controlled by SMBus/I
or DC dimming. The LEDs driving is default to off and the
users will need the SMBus/I
driving and controlling of various parameters that will be
described in this section. Please note that the ISL97671
can also be controlled by an external PWM signal for
PWM dimming without any SMBus/I
so, the users need to pull the SMBCLK and SMBDAT pins
to low or ground the pins permanently if SMBus/I
control is not used. The switching frequency is fixed at
600kHz if SMBus/I
Write Byte
The Write Byte protocol is only three bytes long. The first
byte starts with the slave address followed by the
“command code,” which translates to the “register index”
being written. The third byte contains the data byte that
must be written into the register selected by the
“command code”. A shaded label is used on cycles during
which the slaved backlight controller “owns” or “drives”
the Data line. All other cycles are driven by the “host
master.”
Read Byte
As shown in Figure 28, the four byte long Read Byte
protocol starts out with the slave address followed by
the “command code” which translates to the “register
index.” Subsequently, the bus direction turns around
with the re-broadcast of the slave address with bit 0
indicating a read (“R”) cycle. The fourth byte contains
the data being returned by the backlight controller. That
byte value in the data byte reflects the value of the
register being queried at the “command code” index.
Note the bus directions, which are highlighted by the
1
S
Master to Slave
Slave to Master
Slave Address
1
S
2
C Communications
Master to Slave
Slave to Master
7
2
Slave Address
C is not used.
7
W
1
18
2
C interface to enable the
A
1
2
C interface. To do
W
1
Command
Code
FIGURE 27. WRITE BYTE PROTOCOL
FIGURE 28. READ BYTE PROTOCOL
8
2
1
A
C for PWM
2
C
ISL97671
Command Code
1
A
8
1
S
shaded label that is used on cycles during which the
slaved backlight controller “owns” or “drives” the Data
line. All other cycles are driven by the “host master.”
Slave Device Address
The slave address contains 7 MSB plus one LSB as R/W
bit, but these 8 bits are usually called Slave Address
bytes. As shown in Figure 29, the high nibble of the Slave
Address byte is 0x5 or 0101b to denote the “backlight
controller class.” Bit 3 in the lower nibble of the Slave
Address byte is 1. Bit 0 is always the R/W bit, as
specified by the SMBus/I
document, the device address will always be expressed
as a full 8-bit address instead of the shorter 7-bit address
typically used in other backlight controller specifications
to avoid confusion. Therefore, if the device is in the write
mode where bit 0 is 0, the slave address byte is 0x58 or
01011000b. If the device is in the read mode where bit 0
is 1, the slave address byte is 0x59 or 01011001b.
The backlight controller may sense the state of the pins
at POR or during normal operation - the pins will not
change state while the device is in operation.
SMBus/I
The backlight controller registers are Byte wide and
accessible via the SMBus/I
Their bit assignments are provided in the following
sections with reserved bits containing a default value of “0”.
Slave Address
8
1
A
2
C Register Definitions
R
1
Data byte
8
2
1
A
C protocol. Note: In this
2
C Read/Write Byte protocols.
Data Byte
8
1
A
1
P
1
A
June 24, 2010
FN7631.0
1
P