ISL97671IRZ-T Intersil, ISL97671IRZ-T Datasheet - Page 19

• Manufacturer Part Number: ISL97671IRZ-T
• Description: IC LED DVR PWM CTRL 6CH 20QFN
• Manufacturer: Intersil

Specifications of ISL97671IRZ-T

• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 6
• Internal Driver: Yes
• Type - Primary: Automotive, Backlight
• Type - Secondary: RGB, White LED
• Frequency: 600kHz ~ 1.2MHz
• Voltage - Supply: 4.5 V ~ 26.5 V
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 40mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

ADDRESS
ADDRESS
0x0A
0x00
0x01
0x02
0x03
0x07
0x08
0x09
0x00
0x01
0x02
0x03
FIGURE 29. SLAVE ADDRESS BYTE DEFINITION
DC Brightness
Configuration
Identification
Fault/Status
REGISTER
MSB
Phase Shift
Brightness
PWM Brightness Control
Register
Device Control Register
Fault/Status Register
Identification Register
0
Register
Register
Register
Register
Register
Register
Channel
Register
Control
Control
Control
Output
Device
IDENTIFIER
PWM
Deg
DEVICE
1
REGISTER
Reserved
Reserved
Reserved DirectPWM
Reserved
0
BRTDC7
BIT 7
PANEL
Phase
Equal
BRT7
LED
19
1
Reserved
Reserved
Reserved
ADDRESS
BRTDC6
DEVICE
1
BIT 6
MFG3
Phase
Shift6
BRT6
TABLE 2A. ISL97671 REGISTER LISTING
0
BRT[7..0] = 256 steps of DPWM duty cycle brightness control
PWM_MD = PWM mode select bit (1 = absolute brightness, 0 = % change), default = 0
PWM_SEL = Brightness control select bit (1 = control by PWMI, 0 = control by
SMBus/I
BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0
2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK)
1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK)
BL_STAT = BL status (1 = BL On, 0 = BL Off)
OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK)
THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK)
FAULT = Fault occurred (Logic “OR” of all of the fault conditions)
MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9)
REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins)
TABLE 2B. DATA BIT DESCRIPTIONS
2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN
Reserved
BRTDC5
BIT 5
Phase
MFG2
Shift5
BRT5
0
CH5
0
2
LSB
R/W
C), default = 0
Reserved Reserved PWM_MD
BRTDC4
ISL97671
BIT 4
Phase
Shift4
MFG1
BRT4
CH4
1
BRTDC3
BIT 3
Phase
MFG0
Shift3
BRT3
CH3
1
DATA BIT DESCRIPTIONS
BRTDC2
BIT 2
Phase
Shift2
REV2
BRT2
FSW
CH2
PWM_SEL
BRTDC1
BIT 1
Phase
Shift1
REV1
VSC1
BRT1
CH1
BRTDC0
BL_CTL
BIT 0
FAULT
Phase
Shift0
BRT0
REV0
VSC0
CH0
DEFAULT
VALUE
0xC8
0x00
0xFF
0x00
0x00
0xFF
0x1F
0x3F
SMBUS/I
PROTOCOL
June 24, 2010
Read Only
Read Only
Read and
Read and
Read and
Read and
Read and
Read and
Write
Write
Write
Write
Write
Write
FN7631.0
2
C