X9521V20I Intersil, X9521V20I Datasheet - Page 7

• Manufacturer Part Number: X9521V20I
• Description: IC LASR CTRLR 2CHAN 5.5V 20TSSOP
• Manufacturer: Intersil
• Type: Laser Diode Controller (Fiber Optic)r

Specifications of X9521V20I

• Number Of Channels: 2
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 1.5mA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: X9521V20I-A; X9521V20I-A

If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
the associated NVM register remains unchanged. There-
fore, when Vcc to the device is powered down then back
up, the “wiper position” reverts to that last written to the
DCP using a nonvolatile write operation.
DCP Write Operation
A write to DCPx (x = 1,2) can be performed using the
three byte command sequence shown in Figure 9.
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Reg-
ister must first be set (See “BL1, BL0: Block Lock protec-
tion bits - (Nonvolatile)” on page 12.)
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9521 after the Slave Address, if it has
been received correctly.
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
†
WT
This bit has no effect when a Read operation is being performed.
0
1
WRITE TYPE
†
S
T
A
R
T
Figure 8.
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
Select a Nonvolatile Write operation to be per-
formed on the DCP pointed to by bits P1 and P0
I7
WT
1
0
I6
SLAVE ADDRESS BYTE
0
1
I5
0
Instruction Byte Format
0
I4
1
0
Description
7
1
I3
0
1
I2
0
Figure 9.
0
DCP SELECT
I1
A
C
K
P1
WT
I0
P0
0
INSTRUCTION BYTE
DCP Write Command Sequence
0
0
X9521
0
0
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9521.
Following the Instruction Byte, a Data Byte is issued to
the X9521 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has
been issued on SDA (See Figure 25).
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. There-
fore, the Data Byte 00001111 (15 10 ) corresponds to set-
ting the “wiper terminal” to tap position 15. Similarly, the
Data Byte 00011100 (28 10 ) corresponds to setting the
“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1” . An example of a simple C lan-
guage function which “translates” between the tap posi-
tion (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2” .
It should be noted that all writes to any DCP of the X9521
are random in nature. Therefore, the Data Byte of con-
secutive write operations to any DCP can differ by an
arbitrary number of bits. Also, setting the bits (P1 = 0,
P1 - P0
P1 P0
0
0
1
1
0
1
0
1
A
C
K
DCPx
D7 D6 D5 D4 D3 D2 D1 D0
x = 1
x = 2
DATA BYTE
# Taps
100
256
Reserved
Reserved
Refer to Appendix 1
Max. Data Byte
September 21, 2010
FFh
A
C
K
S
T
O
P
FN8207.2