X9521V20I Intersil, X9521V20I Datasheet - Page 12

• Manufacturer Part Number: X9521V20I
• Description: IC LASR CTRLR 2CHAN 5.5V 20TSSOP
• Manufacturer: Intersil
• Type: Laser Diode Controller (Fiber Optic)r

Specifications of X9521V20I

• Number Of Channels: 2
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 1.5mA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: X9521V20I-A; X9521V20I-A

CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register pro-
vides the user with a mechanism for changing and
reading the status of various parameters of the
X9521 (See Figure 17).
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CON-
STAT register retain their stored values even when Vcc
is powered down, then powered back up. The volatile
bits however, will always power-up to a known logic state
“0” (irrespective of their value at power-down).
A detailed description of the function of each of the CON-
STAT register bits follows:
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the
entire X9521 device. This bit must first be enabled before
ANY write operation (to DCPs, EEPROM memory array,
or the CONSTAT register). If the WEL bit is not first
enabled, then ANY proceeding (volatile or nonvolatile)
write operation to DCPs, EEPROM array, as well as the
CONSTAT register, is aborted and no ACKNOWLEDGE
is issued after a Data Byte.
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
CS7
CS7 - CS5
BL1 - BL0
0
Figure 17. CONSTAT Register Format
RWEL
Bit(s)
WEL
CS0
CS6
0
CS5
0
Always “0”(RESERVED)
Sets the Block Lock partition
Register Write Enable Latch bit
Write Enable Latch bit
Always “0” (RESERVED)
CS4
BL1
NV
12
BL0
CS3
Description
NV
CS2
RWEL
CS1
WEL
CS0
0
X9521
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by
writing 00000010 to the CONSTAT register. Once
enabled, the WEL bit remains set to “1” until either it is
reset to “0” (by writing 00000000 to the CONSTAT regis-
ter) or until the X9521 powers down, and then up again.
Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition is
executed in the CONSTAT Write command sequence
(See Figure 18).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9521. Therefore, in order to write
to any of the bits of the CONSTAT Register (except
WEL), the RWEL bit must first be set to “1”. The RWEL
bit is a volatile bit that powers up in the disabled, LOW
(“0”) state.
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT
Register Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of three cases:
—After a successful write operation to any bits of
—When the X9521 is powered down.
—When attempting to write to a Block Lock protected
BL1, BL0: Block Lock protection bits - (Nonvolatile)
The Block Lock protection bits (BL1 and BL0) are
used to:
—Inhibit a write operation from being performed to cer-
—Inhibit a DCP write operation (changing the “wiper
the CONSTAT register has been completed (See
Figure 18).
region of the EEPROM memory (See "BL1, BL0: Block
Lock protection bits - (Nonvolatile)", below).
tain addresses of the EEPROM memory array
position”).
September 21, 2010
FN8207.2