ISL6112IRZA Intersil, ISL6112IRZA Datasheet - Page 19

• Manufacturer Part Number: ISL6112IRZA
• Description: IC PWR CNTRLR DUAL SLT 48-QFN
• Manufacturer: Intersil
• Type: Hot-Swap Controllerr

Specifications of ISL6112IRZA

• Applications: General Purpose, PCI Express
• Internal Switch(s): No
• Voltage - Supply: 3.3V, 12V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ISL6112 Register Set and Programmer’s Model
Detailed Register Descriptions
Control Register, Slot A (CNTRLA)
8-Bits, Read/Write
CNTRLA
CNTRLB
STATA
STATB
CS
Reserved
AUXAPG
MAINAPG
D[5]
D[4]
D[3]
FORCE_A
ENABLE
MAINA
VAUXA
Power-Up Default Value:
Read Command_Byte Value (R/W):
The power-up default value is 00
NOTES:
6. The state of the PWRGDA pin is the logical AND of the values of the AUXAPG and the MAINAPG bits, except when FORCE_ONA is asserted.
7. The values of the MAINAPG and AUXAPG register bits are not affected by FORCE_ONA, but will instead continue to read as high if power is
BIT(s)
read-only
AUXAPG
If FORCE_ONA is asserted (the pin is pulled low), and FORCE_AENABLE is set to a logic zero, the PWRGDA pin will be unconditionally
forced to its open-drain (“Power Not Good”) state.
“Good,” and as low if the conditions which indicate that power is good are not met.
D[7]
LABEL
MAIN output power-good status, Slot A
AUX output power-good status, Slot A
Reserved
Reserved
Reserved
Allows or inhibits the operation of the FORCE_ONA input pin
MAIN enable control, Slot A
VAUX enable control, Slot A
MAINAPG
read-only
Control Register Slot A
Control Register Slot B
Slot A Status
Slot B Status
Common Status Register
Reserved/Do Not Use
D[6]
TARGET REGISTER
19
h
. Slot is disabled upon power-up, i.e., all supply outputs are off.
Reserved
read only
FUNCTION
DESCRIPTION
TABLE 5. CONTROL REGISTER, SLOT A (CNTRLA)
D[5]
TABLE 4. ISL6112 REGISTER ADDRESSES
0000 0010
0000 0000
b
b
Reserved
read only
= 00
= 02
D[4]
ISL6112
h
h
07h - FFh
02h
03h
04h
05h
06h
read-only
Reserved
D[3]
1 = Power-is-Good (VAUXA Output is above its UVLO
threshold)
1 = Power-is-Good (MAINA Outputs are above their UVLO
thresholds)
Always read as zero
Always read as zero
Always read as zero
0 = FORCE_ONA is enabled
1 = FORCE_ONA is disabled
0 = Off, 1 = On
0 = Off, 1 = On
READ
COMMAND BYTE VALUE
FORCE
read/write
ENABLE
D[2]
02h
03h
04h
05h
06h
07h - FFh
_A
OPERATION
WRITE
read/write
MAINA
D[1]
00h
00h
00h
00h
xxxx 0000b
Undefined
September 28, 2007
POWER-ON
DEFAULT
read/write
VAUXA
D[0]
FN6456.0