LTC4252A-1IMS Linear Technology, LTC4252A-1IMS Datasheet - Page 9

• Manufacturer Part Number: LTC4252A-1IMS
• Description: IC CTRLR HOTSWAP NEG VOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4252A-1IMS

• Applications: General Purpose
• Internal Switch(s): No
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Family Name: LTC4252A-1
• Package Type: MSOP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 0.86mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PI FU CTIO S
V
to the positive side of the supply through a dropping
resistor. A shunt regulator clamps V
undervoltage lockout (UVLO) circuit holds GATE low until
the V
UV is high, OV is low and V
starts an initial timing cycle before initiating a GATE ramp-
up. If V
immediately.
PWRGD (Pin 2/Not Available): Power Good Status Out-
put (MS only). At start-up, PWRGD latches low if DRAIN
is below 2.385V and GATE is within 2.8V of V
status is reset by UV, V
timeout. This pin is internally pulled high by a 58µA current
source.
SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp
inrush current during start up, thereby effecting control
over di/dt. A 20x attenuated version of the SS pin voltage
is presented to the current limit amplifier. This attenuated
voltage limits the MOSFET’s drain current through the
sense resistor during the soft-start current limiting. At the
beginning of a start-up cycle, the SS capacitor (C
ramped by a 22µA (28µA for the LTC4252A) current
TYPICAL PERFOR A CE CHARACTERISTICS
IN
62
61
60
59
58
57
56
55
U
(Pin 1/Pin 1): Positive Supply Input. Connect this pin
–55 –35 –15
IN
I
PGH
V
(MS ONLY)
IN
PWRGD
pin is greater than V
drops below approximately 8.2V, GATE pulls low
vs Temperature
U
= 0V
TEMPERATURE °(C)
5
25
U
45
IN
65
(UVLO) or a circuit breaker fault
IN
(MS/MS8)
85 105 125
LKO
W
comes out of UVLO, TIMER
4252-1/2 G38
, overriding UV and OV. If
U
IN
at 13V. An internal
220
210
200
190
180
170
160
150
–55 –35 –15
IN
t
SS
SS PIN FLOATING,
V
SS
. PWRGD
vs Temperature
RAMPS FROM 0.2V TO 2V
SS
) is
TEMPERATURE (°C)
5
25
source. The GATE pin is held low until SS exceeds 20 • V
= 0.2V. SS is internally shunted by a 100k resistor (R
which limits the SS pin voltage to 2.2V(50k resistor and
1.4V for the LTC4252A). This corresponds to an analog
current limit SENSE voltage of 100mV (60mV for the
LTC4252A). If the SS capacitor is omitted, the SS pin
ramps up in about 180µs. The SS pin is pulled low under
any of the following conditions: in UVLO, in an undervolt-
age condition, in an overvoltage condition, during the
initial timing cycle or when the circuit breaker fault times
out.
SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense
Pin. Load current is monitored by a sense resistor R
connected between SENSE and V
three steps. If SENSE exceeds V
breaker comparator activates a (230µA + 8 • I
pull-up current. If SENSE exceeds V
limit amplifier pulls GATE down to regulate the MOSFET
current at V
circuit, SENSE may overshoot. If SENSE reaches V
(200mV), the fast current limit comparator pulls GATE low
with a strong pull-down. To disable the circuit breaker and
current limit functions, connect SENSE to V
45
65
LTC4252A-1/LTC4252A-2
85 105 125
4252-1/2 G27
ACL
LTC4252-1/LTC4252-2
/R
S
. In the event of a catastrophic short-
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–55
t
vs Temperature
PLLUG
t
–35
PLLUG
t
PHLOG
–15
and t
CB
TEMPERATURE (°C)
ACL
5
EE
PHLOG
(50mV), the circuit
, and controlled in
25
, the analog current
45
EE
65
DRN
.
85 105
) TIMER
4252-1/2 G24
425212fb
9
SS
FCL
125
OS
S
)