LTC4252A-1IMS Linear Technology, LTC4252A-1IMS Datasheet - Page 24

• Manufacturer Part Number: LTC4252A-1IMS
• Description: IC CTRLR HOTSWAP NEG VOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4252A-1IMS

• Applications: General Purpose
• Internal Switch(s): No
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Family Name: LTC4252A-1
• Package Type: MSOP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 0.86mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
Undervoltage Timing
In Figure 11 when UV pin drops below V
the LTC4252 shuts down with TIMER, SS and GATE all
pulling low. If current has been flowing, the SENSE pin
voltage decreases to zero as GATE collapses. When UV
recovers and clears V
cycle begins followed by a GATE start-up cycle.
V
The V
similar timing behavior as the UV pin timing except it looks
for V
start. In an undervoltage lockout condition, both UV and
OV comparators are held off. When V
lockout, the UV and OV comparators are enabled.
Undervoltage Timing with Overvoltage Glitch
In Figure 12, both UV and OV pins are connected together.
When UV clears V
24
IN
Undervoltage Lockout Timing
IN
IN
< (V
undervoltage lockout comparator, UVLO, has a
LKO
PWRGD
TIMER
SENSE
DRAIN
GATE
UV
SS
– V
UVHI
U
LKH
UV DROPS BELOW V
1
UVHI
(time point 1), an initial timing cycle
V
V
GATEL
) to shut down and V
UVLO
V
UVHI
U
(time point 2), an initial timer
UV CLEARS V
Figure 11. Undervoltage Timing (All Waveforms are Referenced to V
2
UVLO
W
. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
UVHI
IN
UVLO
5.8µA
, CHECK OV CONDITION, GATE < V
exits undervoltage
INITIAL TIMING
(time point 1),
IN
20 • (V
20 • (V
U
> V
V
ACL
TMRH
LKO
CB
20 • V
V
+ V
+ V
TMRL
OS
OS
OS
to
)
)
3 4 56
58µA
TIMER CLEARS V
GATEL
230µA + 8 • I
starts. If the system bus voltage overshoots V
shown at time point 2, TIMER discharges. At time point 3,
the supply voltage recovers and drops below the V
threshold. The initial timing cycle restarts, followed by a
GATE start-up cycle.
Overvoltage Timing
During normal operation, if the OV pin exceeds V
shown at time point 1 of Figure 13, the TIMER and PWRGD
status are unaffected. Nevertheless, SS and GATE pull
down and the load is disconnected. At time point 2, OV
recovers and drops below the V
start-up cycle begins. If the overvoltage glitch is long
enough to deplete the load capacitor, a full start-up cycle
as shown between time points 4 through 7 may occur.
Circuit Breaker Timing
In Figure 14a, the TIMER capacitor charges at 230µA if the
SENSE pin exceeds V
SENSE pin drops below V
START-UP
, SENSE < V
GATE
7
58µA
8 9
DRN
TMRL
10 11
CB
, SS < 20 • V
, CHECK GATE < V
V
V
V
V
V
IN
ACL
CB
DRNCL
DRNL
– V
GATEH
5.8µA
OS
AND TIMER < V
GATEL
CB
but V
, SENSE < V
CB
EE
)
TMRL
before TIMER reaches the
DRN
5.8µA
CB
4252-1/2 F11
OVLO
AND SS < 20 • V
is less than 5V. If the
threshold. A GATE
OS
OVHI
OVHI
425212fb
OVLO
as
as