LTC4253CGN Linear Technology, LTC4253CGN Datasheet - Page 10

• Manufacturer Part Number: LTC4253CGN
• Description: IC HOT SWAP CONTRLR -48V 16-SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4253CGN

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 11.2 V ~ 14.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pin FuncTions
LTC4253/LTC4253A
TIMER (Pin 13): Timer Input. Timer is used to generate
an initial timing delay at start-up, and to delay shutdown
in the event of an output overload (circuit breaker fault).
Timer starts an initial timing cycle when the following
conditions are met: RESET is low, UV is high, OV is low,
V
than V
current of 5µA then charges C
If C
TIMER quickly pulls low and GATE is activated.
If SENSE exceeds 50mV while GATE is high, a circuit breaker
cycle begins with a 200µA pull-up current charging C
DRAIN is approximately 7V (6V for the LTC4253A) dur-
ing this cycle, the timer pull-up has an additional current
of 8 • I
reaches 4V, a 5µA pull-down current slowly discharges
the C
the V
quickly pulls low and PWRGD1 pulls high. TIMER latches
high with a 5µA pull-up source. This latched fault may be
cleared by driving RESET high until TIMER is pulled low.
Other ways of clearing the fault include pulling the V
momentarily below (V
an external device or pulling UV below 2.925V (2.756V
for the LTC4253A).
10
IN
T
clears UVLO, TIMER pin is low, GATE pin is lower
charges to V
TMRH
T
GATEL
. In the event that C
DRN
(4V) threshold, the circuit breaker trips, GATE
. If SENSE drops below 50mV before TIMER
, SS < 0.2V, and V
TMRH
LKO
(4V), the timing cycle terminates.
– V
T
LKH
SENSE
eventually integrates up to
T
, generating a time delay.
), pulling TIMER low with
– V
EE
< V
CB
. A pull-up
IN
T
pin
. If
SQTIMER (Pin 14): Sequencing Timer Input. The sequenc-
ing timer provides a delay t
ing. This delay is adjusted by connecting an appropriate
capacitor to this pin. If the SQTIMER capacitor is omitted,
the SQTIMER pin ramps from 0V to 4V in about 300µs.
EN3 (Pin 15): Power Good Status Output Three Enable.
This is a TTL compatible input that is used to control the
PWRGD3 output. When EN3 is driven low, PWRGD3 will
go high. When EN3 is driven high, PWRGD3 will go low
provided PWRGD2 has been active for for more than one
power good sequence delay (t
control the power good sequence. This pin is internally
pulled low by a 120µA current source.
PWRGD3 (Pin 16): Power Good Status Output Three.
Power good sequence starts with PWRGD1 latching active
low. PWRGD3 will latch active low after EN3 goes high
and after one power good sequence delay t
by the sequencing timer from the time PWRGD2 goes
low, whichever comes later. PWRGD3 is reset by PWRGD1
going high or EN3 going low. This pin is internally pulled
high by a 50µA current source.
SQT
for the power good sequenc-
SQT
). EN3 can be used to
SQT
provided
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