LT4256-3IGN Linear Technology, LT4256-3IGN Datasheet - Page 16

• Manufacturer Part Number: LT4256-3IGN
• Description: IC CTRLR HOTSWP HV DETECT 16SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LT4256-3IGN

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 10.8 V ~ 80 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LT4256-3
In some applications it may be possible for V
below ground (due to the parasitic trace inductance).
Higher current applications, especially where the output
load is physically far away from the LT4256-3 will be more
susceptible to these transients. This is normal and the
LT4256-3 has been designed to allow for some ringing
below ground. However, if the application is such that
V
occur to the LT4256-3 and an external diode, D2, from
ground (anode) to V
the circuit as shown in Figure 15 (it is critical that the
reverse breakdown voltage of the diode be higher than the
highest expected V
ground to V
reduce the amount of ringing on V
enough for some applications.
During a fault condition, the LT4256-3 pulls down on
GATE with a switch capable of sinking about 62mA. Once
GATE drops below the output voltage by a diode forward
voltage, the external Zener will forward bias and V
also be discharged to GND. In addition to the GATE
capacitance, the output capacitance will be discharged
through the LT4256-3.
In applications utilizing very large external N-channel
MOSFETs, the possibility exists for the MOSFET to turn on
when initially inserted into a live backplane (before the
16
OUT
can ring more than 3V below ground, damage may
OUT
directly at the LT4256-3 pins can help
GND
V
48V
U
CC
OUT
CC
voltage). A capacitor placed from
(cathode) will have to be added to
0.01µF
U
(SHORT PIN)
C3
Figure 15. Negative Output Voltage Protection Diode Application
OUT
W
R1
64.9k
R2
4.02k
R3
4.02k
but it may not be
C2
33nF
D2
SMAT70A
1
2
4
9
UV
OV
OPEN
TIMER
OUT
V
CC
U
LT4256-3
16
0.010Ω
GND
R5
OUT
to ring
8
SENSE
PWRGD
RETRY
GATE
V
will
15
OUT
FB
13
12
10
7
5
IRF540
LT4256-3 becomes active and pulls down on GATE). This
is due to the MOSFET intrinsic drain to gate capacitance
forcing current into R7 and C1 when the drain voltage
steps up from ground to V
time. To alleviate this situation, a diode, D3, should be put
across R7 with the cathode connected to C1 as shown in
Figure 16.
Whenever the LT4256-3 turns the MOSFET off, GATE pulls
the MOSFET gate to ground with an open collector capable
of sinking 62mA. If the output is held up by a large
reservoir capacitor, the stored energy is dissipated in the
pull-down transistor via a sneak path through the (now
forward biased) Zener, D1. The LT4256-3 has a propri-
etary feature that reduces on-chip power dissipation by
sensing when the MOSFET is off and reducing the pull-
down current significantly. See V
information about using this feature.
V
The LT4256-3 has a proprietary feature that reduces
power dissipation by sensing when the MOSFET is off and
reducing the pull-down current significantly. As the GATE
pin is discharged during any fault, the LT4256-3 monitors
the GATE pin and V
V
about 130µA.
Q1
UV = 36V
OV = 73V
PWRGD = 40V
GATE
OUT
R7
100Ω
R6
10Ω
C1
10nF
, the pull-down current is reduced from 62mA to
Turn-Off
D1
CMPZ5241BS
11V
OUT
R9
4.02k
R8
36.5k
4256 F14
pin. When the GATE pin is 2V below
R4
51k
+
CC
with an extremely fast rise
D3
MRA4003T3
C
L
V
48V
4A
GATE
OUT
Turn-Off for more
42563fa