LT4256-3IGN Linear Technology, LT4256-3IGN Datasheet - Page 15

• Manufacturer Part Number: LT4256-3IGN
• Description: IC CTRLR HOTSWP HV DETECT 16SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LT4256-3IGN

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 10.8 V ~ 80 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
This open FET condition can be falsely signalled during
start-up if the load is not activated until after PWRGD goes
high. To avoid this false indication, OPEN and PWRGD
should not be polled for a period of time, t
by:
This can be accomplished either by a microcontroller (if
available) or by placing an RC filter as shown in Figure 13.
Once the OPEN voltage exceeds the monitoring logic thresh-
old, V
is signalled. In order to prevent a false indication, the RC
product should be set with the following equation:
Another condition that can cause a false indication is if the
LT4256-3 goes into current limit during start-up. This will
cause t
LT4256-3 stays in current limit long enough for TIMER to
fully charge up to its threshold, the LT4256-3 will either
latch off (RETRY = 0) or go into the current limit hiccup
mode (RETRY = floating). In either case, an open FET
condition will be falsely signalled. If the LT4256-3 does go
into current limit during start-up, C1 can be increased (see
Power-Up Sequence).
RC
t
STARTUP
THRESH
>
STARTUP
Figure 13. Delay Circuit for OPEN FET Detection
OPEN COLLECTOR
32
PULL-DOWN
INTERNAL
µ
, and PWRGD is low, an open FET condition
=
A
⎛
⎜
⎝
3
LT4256-3
ln
to be longer than calculated. Also, if the
•
⎛
⎜
⎝
32
V
3
V
U
CC
•
LOGIC
µ
V
A
•
CC
C
V
OPEN
1
U
LOGIC
•
–
C
V
1
THRESH
4
V
LOGIC
W
R
⎞
⎟
⎠
C
⎞
⎟
⎠
TO
MONITORING
LOGIC
STARTUP
4256 F13
U
, given
(10)
(9)
Supply Transient Protection
The LT4256-3 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 80V. However,
voltage transients above 100V may cause permanent
damage. During a short-circuit condition, the large change
in currents flowing through the power supply traces can
cause inductive voltage transients which could exceed
100V. To minimize the voltage transients, the power trace
parasitic inductance should be minimized by using wider
traces or heavier trace plating and a bypass capacitor
should be placed between V
sor (TransZorb
from voltage transients.
GATE Pin
A curve of gate drive vs V
is clamped to a maximum voltage of 12.8V above V
This clamp is designed to withstand the internal charge
pump current. An external Zener diode must be used as
shown in all applications. At a minimum input supply
voltage of 10.8V, the minimum gate drive voltage is 4.5V.
When the input supply voltage is higher than 20V, the gate
drive voltage is at least 10V and a standard threshold
MOSFET can be used. In applications from 12V to 15V
range, a logic level MOSFET must be used.
TransZorb is a registered trademark of General Instruments, GSI.
13
12
11
10
9
8
7
6
5
4
3
10
®
) at the input can also prevent damage
20
Figure 14. ∆V
30
40
CC
V
CC
CC
is shown in Figure 14. GATE
(V)
50
GATE
and GND. A surge suppres-
vs V
60
CC
70
LT4256-3
4256 F14
80
15
42563fa
OUT
.