LTC4214-2CMS Linear Technology, LTC4214-2CMS Datasheet - Page 23

• Manufacturer Part Number: LTC4214-2CMS
• Description: IC CTRLR HOTSWAP NEGVOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4214-2CMS

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 6 V ~ 16 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Linear Misc Type: Negative Low Voltage
• Family Name: LTC4214-2
• Package Type: MSOP
• Operating Supply Voltage (min): -6V
• Operating Supply Voltage (max): -16V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Depth (mm): 3mm
• Product Height (mm): 0.86mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
V
The V
similar timing behavior as the UV pin timing except it looks
for V
start. In an undervoltage lockout condition, both UV and
OV comparators are held off. When V
lockout, the UV and OV comparators are enabled.
IN
Undervoltage Lockout Timing
IN
IN
< (V
undervoltage lockout comparator, UVLO, has a
PWRGD
TIMER
SENSE
DRAIN
UV/OV
GATE
LKO
SS
Figure 11. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to V
– V
V
UV/OV CLEARS V
OVHI
1
U
LKH
V
UVHI
UV/OV OVERSHOOTS V
2
) to shut down and V
UV/OV DROPS BELOW V
U
3
V
V
UVHI
GATEL
OVHI
, CHECK OV CONDITION, GATE < V
– V
OVHST
W
OVHI
IN
5 A
INITIAL TIMING
exits undervoltage
AND TIMER ABORTS INITIAL TIMING CYCLE
OVHI
– V
IN
20 • (V
20 • (V
OVHST
U
> V
V
ACL
TMRH
CB
20 • V
AND TIMER RESTARTS INITIAL TIMING CYCLE
LKO
V
+ V
+ V
TMRL
GATEL
OS
OS
OS
to
)
)
50 A
, SENSE < V
4 5 67
TIMER CLEARS V
40 A + 8 • I
Undervoltage Timing with Overvoltage Glitch
In Figure 11, both UV and OV pins are connected together.
When UV clears V
cycle starts. If the system bus voltage overshoots V
as shown at time point 2, TIMER discharges. At time point
3, the supply voltage recovers and drops below the V
– V
followed by a GATE start-up cycle.
START-UP
GATE
8
CB
OVHST
50 A
, SS < 20 • V
DRN
9
10
11
TMRL
12
threshold. The initial timing cycle restarts,
, CHECK GATE < V
V
V
V
V
V
IN
ACL
CB
DRNCL
DRNL
LTC4214-1/LTC4214-2
OS
– V
AND TIMER < V
GATEH
5 A
UVHI
GATEL
(time point 1), an initial timing
TMRL
, SENSE < V
5 A
CB
AND SS < 20 • V
4214 F11
EE
)
OS
23
421412f
OVHI
OVHI