NCP1377PG ON Semiconductor, NCP1377PG Datasheet - Page 9

• Manufacturer Part Number: NCP1377PG
• Description: IC CTRLR PWM CM OVP UVLO 8DIP
• Manufacturer: ON Semiconductor

Specifications of NCP1377PG

• Output Isolation: Isolated
• Frequency Range: 100kHz
• Voltage - Input: 8.2 ~ 18 V
• Operating Temperature: 0°C ~ 125°C
• Package / Case: 8-DIP (0.300", 7.62mm), 7 Leads
• Number Of Outputs: 1
• Output Voltage: 18 V
• Output Current: 500 mA
• Mounting Style: Through Hole
• Switching Frequency: 100 KHz
• Maximum Operating Temperature: + 150 C
• Fall Time: 20 ns
• Rise Time: 40 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCP1377PGOS

information to the FB pin while providing the necessary
isolation. It introduces a limitation in how low the skip
level can be adjusted since an optocoupler cannot pull the
FB voltage below its Vce(sat), which is usually around
150 mV. Therefore, in order to take into account
temperature and process variations, it is not recommended
to set up the skip level below 250 mV, which corresponds
to a minimum resistor Rskip of 420 W. The 150 mV is a
much lower level than what will usually be used (it sets the
peak current when entering skip mode at 5% of the
An optocoupler is generally used to transfer the feedback
−1.0
7.0
5.0
3.0
1.0
Figure 21. Core Reset Detection is Done through
RESTARTS
POSSIBLE
a Dedicated Auxiliary Winding Monitoring
together with the sense comparator initiates a new cycle when FB passes the skip level.
Figure 20. When the primary natural ringing becomes too low, the internal TimeOut
Timeout
Timeout
Signal
Signal
Signal
Signal
Drain
Drain
0 V
50 mV
http://onsemi.com
5 ms
9
Current Sense and Timeout Restart
Demag Restart
maximum peak current). If anyway a lower skip threshold
is needed, care must be taken to select an optocoupler with
a Vce(sat) guaranteed to be below the chosen skip level
with enough margin.
Demagnetization Detection
voltage activity on the auxiliary winding. This voltage
features a FLYBACK polarity. The typical detection level
is fixed at 50 mV as exemplified by Figure 21.
COMPARATOR
TO INTERNAL
R
The core reset detection is done by monitoring the
esd
+ R
Figure 22. Internal Pad Implementation
int
R
int
= 28 k
5 ms
2
ESD2
R
esd
1
ESD1
1
4
5
R
dem
4
3
Aux