NCP1219AD100R2G ON Semiconductor, NCP1219AD100R2G Datasheet - Page 18

• Manufacturer Part Number: NCP1219AD100R2G
• Description: IC PWM CONTROLLER 100KHZ 7-SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1219AD100R2G

• Output Isolation: Isolated
• Frequency Range: 95 ~ 105kHz
• Voltage - Input: 9 ~ 20 V
• Power (watts): 920mW
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width) 7 leads
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External Non−Latched Shutdown
pin. An external non−latched shutdown can be easily
implemented by simply pulling FB below the skip level.
This is an inherent feature of the standby skip operation,
allowing additional flexibility in the SMPS design.
non−latched shutdown circuit using a bipolar transistor to
pull the FB pin low.
Table 4. %I
Figure 40 summarizes the operating regions of the FB
Figure 41 shows an example implementation of a
V skip/latch
Figure 39. NCP1219 VSkip/latch Pin Operating
%ICS
Figure 40. NCP1219 Operation Threshold
43 %
12%
37%
43%
25%
0%
V skip
Skip threshold clamped to V
Adjustable V
skip
3 V
Controller is latched
0 V
CSskip
V FB
and Skip Threshold Relationship with R
skip
Fault operation when staying
in this region longer than 118 ms
PWM operation
No DRV pulses
range.
V
Regions
Skip/latch
9.5 V (maximum pin voltage)
V
0.36 V
0.75 V
1.10 V
2.00 V
3.00 V
V
0 V (no skip)
latch
0 V
skip(MAX)
(maximum skip threshold)
skip(MAX)
0.36 V
0.75 V
1.10 V
1.30 V
1.30 V
V
0 V
skip
http://onsemi.com
18
skip
11.8 kW
52.3 kW
according to Equation 10.
to 1.3 V. Increasing the voltage on the Skip/latch pin
beyond the value of the internal clamp will induce no
further change in the skip level. This prevents the act of
disabling the controller in the presence of an external latch
event from causing it to enter skip mode. The relationship
between %I
summarized in Table 4.
Overload Protection
When an overload (or short circuit) event occurs, the output
voltage collapses and the optocoupler does not conduct
current. This opens the FB pin and V
higher than 3.0 V. Since V
controller activates an error flag and starts a timer, t
(118 ms typical). If the output recovers during this time, the
timer is reset and the device continues to operate normally.
R
Open
0 W
Within the adjustable V
An internal clamp limits the skip threshold (V
skip
Figure 42 details the timer based fault detection circuitry.
–
–
opto
coupler
Figure 41. Example Circuit for Non−Latched
V
CSSKIP
Never skips
Default Skip Threshold
No further increase in Skip threshold
No further increase in Skip threshold
skip
OFF
+
, V
(R
2 V @ (R
Shutdown
lower
Skip/latch
skip
FB
ø R
range, the skip level changes
/3 is greater than 1 V, the
Comment
lower
skip
, V
) ) R
–
–
ø R
FB
skip
skip
is internally pulled
upper
, and R
)
Skip/latch
GND
FB
CS
NCP1219
skip(MAX)
VCC
DRV
(eq. 10)
HV
skip
OVLD
is
)