NCP1219AD100R2G ON Semiconductor, NCP1219AD100R2G Datasheet - Page 15

• Manufacturer Part Number: NCP1219AD100R2G
• Description: IC PWM CONTROLLER 100KHZ 7-SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1219AD100R2G

• Output Isolation: Isolated
• Frequency Range: 95 ~ 105kHz
• Voltage - Input: 9 ~ 20 V
• Power (watts): 920mW
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width) 7 leads
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ramp Compensation
subharmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
continuous conduction mode (CCM) with a duty ratio
greater than 50%. To lower the current loop gain, one
usually injects 50 to 75% of the inductor current down
slope. The NCP1219 generates an internal current ramp
that is synchronized with the clock. This current ramp is
then routed to the CS pin. Figures 32 and 33 depict how the
ramp is generated and utilized. Ramp compensation is
simply formed by placing a resistor, R
pin and the sense resistor.
resistor, R
S
where V
diode drop of the secondary diode, N
secondary turns ratio, and L
the transformer. The value of R
Equation 5,
off,primary
I
Ramp compensation is a known mean to cure
In order to calculate the value of the ramp compensation
ramp(peak)
Figure 32. Internal Ramp Compensation Current
Figure 33. Inserting a Resistor in Series with the
Oscillator
Current
Current Sense Information Provides Ramp
Ramp
Clock
out
0
must be calculated using Equation 4,
ramp
is the converter output voltage, V
Ramp current, I
S
off,primary
, the off time primary current slope,
Compensation
+
ramp
Source
(V
P
out
I
ramp(peak)
is the primary inductance of
ramp
) V
DRV
L
CS
can be calculated using
P
80% of period
f
) @
P
ramp
/N
100% of period
S
N
N
, between the CS
is the primary to
P
S
f
is the forward
time
R
ramp
R
CS
http://onsemi.com
(eq. 4)
15
where R
percentage of the current downslope to be used for ramp
compensation.
100 mA. A frequency of 65 kHz with an 80% maximum
duty ratio corresponds to an 8.1 mA/ms ramp. For a typical
flyback design, let’s assume that the primary inductance is
350 mH, the converter output is 19 V, the V
diode is 1 V and the N
primary current slope is given by Equation 6.
becomes 57 mV/ms. If we select 50% of the downslope as
the required amount of ramp compensation, then we shall
inject 28.5 mV/ms. Therefore, R
Equation 7.
down slope can be used if necessary; however,
overcompensating will degrade the transient response of
the system. The addition of ramp compensation also
reduces the total available output power of the system.
Internal Oscillator
clock signal that sets the DRV signal high and limits the
duty ratio to 80% (typical). The oscillator has a fixed
frequency of 65 kHz or 100 kHz. The NCP1219 employs
frequency jittering to smooth the EMI signature of the
system by spreading the energy of the main switching
component across a range of frequencies. An internal low
frequency oscillator continuously varies the switching
frequency of the controller by ±7.5%. The period of
modulation is 6 ms, typical. Figure 34 illustrates the
oscillator frequency modulation.
The NCP1219 has a peak ramp compensation current of
When projected over an R
Ramp compensation greater than 50% of the inductor
The internal oscillator of the NCP1219 provides the
CS
R
is the current sense resistor and %slope is the
ramp
(V
R
+
ramp
out
S
) V
+
off,primary
L
P
28.5
P
f
)
8.1
:N
I
ramp(peak)
N
N
CS
S
mA
P
S
ms
mV
ms
ratio is 10:1. The off time
of 0.1 W (for example), this
+ 571 mA
+ 3.5 kW
D
R
ramp
CS
f
OSC
@ %slope
is simply equal to
ms
f
of the output
(eq. 5)
(eq. 6)
(eq. 7)