L6566A STMicroelectronics, L6566A Datasheet - Page 35

IC CTRLR OVP UVLO 16SOIC

L6566A

Manufacturer Part Number
L6566A
Description
IC CTRLR OVP UVLO 16SOIC
Manufacturer
STMicroelectronics
Datasheet

Specifications of L6566A

Output Isolation
Isolated
Frequency Range
93 ~ 107kHz
Voltage - Input
8 ~ 23 V
Power (watts)
750mW
Operating Temperature
-40°C ~ 150°C
Package / Case
16-SOIC (0.154", 3.90mm Width)
Output Current
800 mA
Output Power
750 mW
Input Voltage
8 V to 23 V
Operating Temperature Range
- 40 C to + 150 C
Mounting Style
SMD/SMT
Duty Cycle (max)
75 %
Universal Input Mains Range
90÷264Vac - Frequency 45 ÷ 65 Hz
Output Voltage
19 V@4 A continuous operation
Mains Harmonics
Acc. to EN61000-3-2 Class-D
St-by Mains Consumption
Less than 0.25 W @265Vac
Overall Efficiency
Better than 86%
Emi
According to EN55022-Class-B
Safety
According to EN60950
Low Profile Design
25 mm maximum height
Pcb Single Layer
single side, 70 μm, CEM-1, 78x174 mm, Mixed PTH/SMT
For Use With
497-8834 - BOARD DEMO FOR L6563/LL6566A497-6452 - BOARD EVAL FOR L6566B497-6451 - BOARD EVAL FOR L6566B497-6450 - BOARD EVAL FOR L6566B497-6449 - BOARD EVAL FOR L6566A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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L6566A
5.11
OVP block
The OVP function of the L6566A monitors the voltage on the ZCD pin (11) in MOSFET’s
OFF-time, during which the voltage generated by the auxiliary winding tracks converter’s
output voltage. If the voltage on the pin exceeds an internal 5 V reference, a comparator is
triggered, an overvoltage condition is assumed and the device is shut down. An internal
current generator is activated that sources 1 mA out of the VFF pin (15). If the VFF voltage
is allowed to reach 2 Vbe over 5 V, the L6566A will be latched off. See
disable function on page 32
impedance externally connected to pin 15 is so low that the 5+2 V
reached or if some means is provided to prevent that, the device will be able to restart after
the Vcc has dropped below 5 V. Refer to the “Application examples and Ideas” section
(
Figure 22. OVP Function: internal block diagram
Table 7 on page 45
PWM latch
R
S
Q
Q
) for additional hints.
Monostable
M1
to triggering
block
for more details on IC’s behavior under these conditions. If the
2 µs
ZCD
11
40k Ω
5pF
5 V
Monostable
M2
+
-
STROBE
0.5 µs
COUT
OVP
R Q1
S
FF
BE
Application information
threshold cannot be
L6566A
Section 5.9: Latched
counter
2-bit
Counter
reset
Fault
35/51

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