DP8421AV-25 National Semiconductor, DP8421AV-25 Datasheet - Page 52

• Manufacturer Part Number: DP8421AV-25
• Description: IC CTRLR/DVR CMOS PROGRAM 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8421AV-25

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8421AV-25

Number
400a
400b
401
402
403a
403b
403c
403d
404
405
406
407
408
409
410
411
412
413
414
415
416
417
13 0 AC Timing Parameters
Unless otherwise stated V
per bank including trace capacitance (Note 2)
Two different loads are specified
C
C
L
L
e
e
50 pF loads on all outputs except
150 pF loads on Q0–8 9 10 and WE or
tSADSCK1
tSADSCKW
tSCSADS
tPADSRL
tPADSCL0
tPADSCL1
tPADSCL2
tPADSCL3
tSADDADS
tHCKADS
tSWADS
tSBADAS
tHASRCB
tSRCBAS
tWADSH
tPADSD
tSWINADS
tPADSWL0
tPADSWL1
tPCLKDL1
tPADSCV0
Symbol
ADS Asserted Setup to CLK High
ADS Asserted Setup to CLK
(to Guarantee Correct WAIT
or DTACK Output Doesn’t Apply for DTACK0)
CS Setup to ADS Asserted
ADS Asserted to RAS Asserted
ADS Asserted to CAS Asserted
(tRAH
ADS Asserted to CAS Asserted
(tRAH
ADS Asserted to CAS Asserted
(tRAH
ADS Asserted to CAS Asserted
(tRAH
Row Address Valid Setup to ADS
Asserted to Guarantee tASR
ADS Negated Held from CLK High
WAITIN Asserted Setup to ADS
Asserted to Guarantee DTACK0
Is Delayed
Bank Address Setup to ADS Asserted
Row Column Bank Address Held from
ADS Asserted (Using On-Chip Latches)
Row Column Bank Address Setup to
ADS Asserted (Using On-Chip Latches)
ADS Negated Pulse Width
ADS Asserted to DTACK Asserted
(Programmed as DTACK0)
WIN Asserted Setup to ADS Asserted
(to Guarantee CAS Delayed during
Writes Accesses)
ADS Asserted to WAIT Asserted
(Programmed as WAIT0 Delayed Access)
ADS Asserted to WAIT Asserted
(Programmed WAIT 1 2 or 1)
CLK High to DTACK Asserted
(Programmed as DTACK0
Delayed Access)
AREQ Negated to ADS Asserted
to Guarantee tASR
(Non Interleaved Mode Only)
ADS Asserted to Column
Address Valid
(t
RAH
CC
e
e
e
e
e
e
5 0V
15 ns t
15 ns tASC
15 ns tASC
25 ns tASC
25 ns tASC
Parameter Description
g
Mode 1 Access
10% 0 C
ASC
e
e
e
e
e
e
0 ns
(Continued)
0 ns)
0 ns)
10 ns)
0 ns)
10 ns)
k
T
e
A k
0 ns
70 C the output load capacitance is typical for 4 banks of 18 DRAMs
52
C
C
C
H
H
H
e
e
e
b
Min
15
31
11
10
12
38
6
9
0
0
3
10
50 pF loads on all outputs except
125 pF loads on RAS0– 3 and CAS0–3 and
380 pF loads on Q0– 8 9 10 and WE
8420A 21A 22A-20
C
L
Max
106
30
86
96
96
43
35
35
40
83
b
Min
15
31
13
11
10
16
42
6
0
0
3
10
C
H
Max
104
104
114
35
94
43
35
35
40
92
b
Min
13
25
11
10
12
31
5
9
0
0
2
10
8420A 21A 22A-25
C
L
Max
25
75
85
85
95
35
29
29
32
69
b
Min
13
25
14
11
10
17
36
5
0
0
2
10
C
H
Max
102
29
82
92
92
35
29
29
32
78