DP8422AV-25 National Semiconductor, DP8422AV-25 Datasheet - Page 7

• Manufacturer Part Number: DP8422AV-25
• Description: IC CTRLR/DVR CMOS PROGRAM 84PLCC
• Manufacturer: National Semiconductor

Specifications of DP8422AV-25

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8422AV-25

2 5 PORT B ACCESS SIGNALS
2 6 COMMON DUAL PORT SIGNALS
2 7 POWER SIGNALS AND CAPACITOR INPUT
AREQB
ATACKB
GRANTB
LOCK
V
GND
CAP
CLK
DELCLK
2 0 Signal Descriptions
CC
2 8 CLOCK INPUTS
There are two clock inputs to the DP8420A 21A 22A CLK and DELCLK These two clocks may both be tied to the same clock
input or they may be two separate clocks running at different frequencies asynchronous to each other
Name
Pin
Applicable to All)
DP8422A
only
DP8422A
only
DP8422A
only
DP8422A
only
Device (If not
Output
Input
O
O
I
I
I
I
I
I
I
(Continued)
SYSTEM CLOCK This input may be in the range of 0 Hz up to 25 MHz This input is
generally a constant frequency but it may be controlled externally to change
frequencies or perhaps be stopped for some arbitrary period of time
This input provides the clock to the internal state machine that arbitrates between
accesses and refreshes This clock’s positive edges and negative levels are used to
extend the WAIT (DTACK) signals Ths clock is also used as the reference for the
RAS precharge time and RAS low time during refresh
All Port A and Port B accesses are assumed to be synchronous to the system clock
CLK
DELAY LINE CLOCK The clock input DELCLK may be in the range of 6 MHz to
20 MHz and should be a multiple of 2 (i e 6 8 10 12 14 16 18 20 MHz) to have
the DP8420A 21A 22A switching characteristics hold If DELCLK is not one of the
above frequencies the accuracy of the internal delay line will suffer This is because
the phase locked loop that generates the delay line assumes an input clock
frequency of a multiple of 2 MHz
For example if the DELCLK input is at 7 MHz and we choose a divide by 3 (program
bits C0– 2) this will produce 2 333 MHz which is 16 667% off of 2 MHz Therefore the
DP8420A 21A 22A delay line would produce delays that are shorter (faster delays)
than what is intended If divide by 4 was chosen the delay line would be longer
(slower delays) than intended (1 75 MHz instead of 2 MHz) (See Section 10 for more
information )
This clock is also divided to create the internal refresh clock
PORT B ACCESS REQUEST This input asserted will latch the row column and bank
address if programmed and requests an access to take place for Port B If the
access can take place RAS will assert immediately If the access has to be delayed
RAS will assert as soon as possible from a positive edge of CLK
ADVANCED TRANSFER ACKNOWLEDGE PORT B This output is asserted when
the access RAS is asserted for a Port B access This signal can be used to generate
the appropriate DTACK or WAIT type signal for Port B’s CPU or bus
GRANT B This output indicates which port is currently granted access to the DRAM
array When GRANTB is asserted Port B has access to the array When GRANTB is
negated Port A has access to the DRAM array This signal is used to multiplex the
signals R0– 8 9 10 C0– 8 9 10 B0– 1 WIN LOCK and ECAS0– 3 to the DP8422A
when using dual accessing
LOCK This input can be used by the currently granted port to ‘‘lock out’’ the other
port from the DRAM array by inserting wait states into the locked out port’s access
cycle until LOCK is negated
POWER Supply Voltage
GROUND Supply Voltage Reference
CAPACITOR This input is used by the internal PLL for stabilization The value of the
ceramic capacitor should be 0 1 F and should be connected between this input and
ground
7
Description