DP8422AV-25 National Semiconductor, DP8422AV-25 Datasheet - Page 22

• Manufacturer Part Number: DP8422AV-25
• Description: IC CTRLR/DVR CMOS PROGRAM 84PLCC
• Manufacturer: National Semiconductor

Specifications of DP8422AV-25

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8422AV-25

5 0 Refresh Options
5 1 2 Externally Controlled Burst Refresh
To use externally controlled burst refresh the user must
disable the automatic internally controlled refreshes by as-
serting the input DISRFSH The user is responsible for gen-
erating the refresh request by asserting the input RFSH
Pulsing RFSH low sets an internal latch that is used to
produce the internal refresh request The refresh cycle will
By keeping RFSH asserted past the positive edge of CLK
which ends the refresh cycle as shown in Figure 14b the
user will perform another refresh cycle Using this tech-
nique the user can perform a burst refresh consisting of any
number of refresh cycles Each refresh cycle during a burst
refresh will meet the refresh RAS low time and the RAS
precharge time (programming bits R0–1)
FIGURE 14a Single External Refreshes (2 Periods of RAS Low during Refresh Programmed)
FIGURE 14b External Burst Refresh (2 Periods of RAS Precharge
2 Periods of Refresh RAS Low during Refresh Programmed)
(Continued)
22
Figure 14a If an access to DRAM is in progress or pre-
take place on the next positive edge of CLK as shown in
charge time for the last access has not been met the re-
fresh will be delayed Since pulsing RFSH low sets a latch
the user does not have to keep RFSH low until the refresh
starts When the last refresh RAS negates the internal re-
fresh request latch is cleared
If the user desires to burst refresh the entire DRAM (all row
addresses) he could generate an end of count signal (burst
refresh
DP8420A 21A 22A high address outputs (Q7 Q8 Q9 or
Q10) and the RFIP output The Qn outputs function as a
decode of how many row addresses have been refreshed
(Q7
freshes Q10
e
128 refreshes Q8
finished)
e
1024 refreshes)
by
e
looking
256 refreshes Q9
at
one
TL F 8588– 64
TL F 8588– 65
e
of
512 re-
the