EPC1213LC20 Altera, EPC1213LC20 Datasheet - Page 37

• Manufacturer Part Number: EPC1213LC20
• Description: IC CONFIG DEVICE 212KBIT 20-PLCC
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC1213LC20

• Programmable Type: OTP
• Memory Size: 212kb
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-PLCC
• For Use With: PLMJ1213 - PROGRAMMER ADAPTER 20 PIN J-LEAD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-2188-5

Concurrent Configuration
Supported Schemes and Guidelines
© December 2009 Altera Corporation
S52014-2.5
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This chapter describes the latest enhanced configuration device flash memory
standard with a feature-rich configuration controller. A single-chip configuration
solution provides you with several new and advanced features that significantly
reduce configuration times. This chapter discusses the hardware and software
implementation of enhanced configuration device features such as concurrent and
dynamic configuration, data compression, clock division, and an external flash
memory interface. Enhanced configuration devices include EPC4, EPC8, and EPC16
devices.
Configuration data is transmitted from the enhanced configuration device to the
SRAM-based device on the DATA lines. The DATA lines are outputs on the enhanced
configuration devices, and inputs to the SRAM-based devices.
These DATA lines correspond to the Bitn lines in the Convert Programming Files
window in the Altera
Object File (.sof) to use Bit0 in the Quartus II software, that .sof will be transmitted
on the DATA[0] line from the enhanced configuration device to the SRAM-based
device.
There are several different ways to configure Altera SRAM-based programmable logic
devices (PLDs) with enhanced configuration devices:
■
■
■
■
■
Additionally, you can use these configuration schemes in conjunction with the
dynamic configuration option (previously called page mode operation) for
sophisticated configuration setups.
FPP configuration mode uses the eight DATA[7..0] lines from the enhanced
configuration device, which can be used to configure APEX
devices. To decrease configuration time, FPP configuration provides eight bits of
configuration data per clock cycle to the target device.
For more information about configuration schemes, refer to the
Devices (EPC4, EPC8, and EPC16) Data
Devices.
1-bit passive serial (PS)
2-bit PS
4-bit PS
8-bit PS
Fast passive parallel (FPP)
®
Quartus
®
2. Altera Enhanced Configuration
II software. For example, if you specify a SRAM
Sheet, or
Configuring Stratix & Stratix GX
Configuration Handbook (Complete Two-Volume Set)
™
II and Stratix
Enhanced Configuration
Devices
®
series