MCM69C432TQ20 Freescale Semiconductor, MCM69C432TQ20 Datasheet - Page 7

• Manufacturer Part Number: MCM69C432TQ20
• Description: IC CAM 1MB 50MHZ 100LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MCM69C432TQ20

• Format - Memory: RAM
• Memory Type: CAM
• Memory Size: 1M (16K x 64)
• Speed: 50MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MOTOROLA FAST SRAM
memory (CAM) that can contain 16K entries of 64 bits each.
The widths of the match field and the output field are pro-
grammable, and the match time is designed to be 180 ns. As
a result, the MCM69C432 is well suited for datacom
applications such as Virtual Path Identifier/Virtual Circuit
Identifier (VPI/VCI) translation in ATM switches up to OC12
(622 Mbps) data rates and Media Access Control (MAC)
address lookup in Ethernet/Fast Ethernet bridges. The
match duty cycle of the MCM69C432 is determined by the
user, with a trade–off between the match request rate and
the rate of entries added to/deleted from the CAM. With the
minimum required 40 ns of idle time between matches, a
typical value of 555 insertions or deletions per second can be
made. See Figure 3 for a graph of the relationship between
insertion/deletion pairs and match duty cycle.
input word through MQ bus and compares it to all the entries
in its CAM table. The MC pin is always asserted after the
comparisons have been made. If a match is found, the MS
pin is asserted, and the data associated with the matching
entry is output on the MQ bus. If no match is found, the MQ
bus remains in a high–impedance state to facilitate depth
expansion via the cascading of multiple CAMs.
start–up functions must be performed. First, the output width
and match width must be designated by setting the
global–mask register. Second, a choice must be made
between buffered–entry mode and fast–entry mode. Next,
the 64–bit match/output data pairs must be loaded into the
table. Depending on the entry mode of choice, the table may
have to be initialized. Optionally, the “almost full” point may
be set to provide warning of impending table overflow.
mask register. The mask bits that are 0 correspond to the bits
that are used in the match operation.Typically, the bits that
are used in matching are the high order bits in the 64–bit
CAM table entries, and the bits that are used as outputs are
the low order bits. While any of the bits can be defined as
match bits, the low order 32 bits of an entry are always driven
on the MQ bus as output data.
entry and latency before matching operations can begin. In a
typical application, the fast–entry mode will be used to load
the initial values into the CAM table. Subsequently, the
initialize–table operation, which takes 80 ms, must be
executed to establish the required linkages and relationships
among the entries. After match operations have begun, the
buffered–entry mode should be used to enter new values
dynamically; even one addition in fast–entry mode will dis-
able matching until the table is reinitialized. Table insertions
using the buffered–entry mode and the fast–entry mode
actually take the same amount of time unless the entry
queue is full. The capacity of the queue is 14 entries.
loaded. Each 64–bit entry is constructed by writing a 16–bit
value to each of the four I/O registers in the control port of the
MCM69C432. The insertion can then be processed. After all
the start–up entries have been loaded into the CAM table,
The MCM69C432 is a flexible content–addressable
In its basic operating mode, the MCM69C432 reads a data
Before the basic operating mode can be entered, several
The input bits to be compared are defined by the global–
The choice of entry mode is a trade–off between speed of
After the entry mode choice is made, the table can be
FUNCTIONAL DESCRIPTION
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the initialization operation is run if required. Normal matching
operations can then begin. A delete operation is provided to
remove stale data from the CAM table.
instruction set. When an error occurs, its corresponding code
is written into the error register and the error bit in the flag
register is set. The error bit is cleared and the error register is
set to FFFF 16 by the next write to the operation register.
MCM69C432’s control port: I/O registers, an operation reg-
ister, and result/condition code registers. Each register is
16 bits in length.
FLAG BIT DEFINITIONS
ERROR CODES
REGISTER NAME
I/O REGISTER 0
I/O REGISTER 1
I/O REGISTER 2
I/O REGISTER 3
OPERATION REGISTER
FLAG REGISTER
ERROR CODE REGISTER
INTERRUPT REGISTER
Several error codes are defined in the details of the
Three types of registers are accessible through the
Bit 0: 1 = At least one interrupt enabled,
Bit 1: 1 = Last control port match successful,
Bit 2: 1 = Table initialized, 0 = Table not initialized
Bit 3: 1 = Buffered–entry mode, 0 = fast–entry mode
Bit 4: 1 = Entry queue empty,
Bit 5: 1 = Entry queue full, 0 = Entry queue not full
Bit 6: 1 = CAM table full, 0 = CAM table not full
Bit 7: 1 = Error condition set, 0 = No error
Bit 8: 1 = Table almost full, 0 = Table not almost full
Bit 9: 1 = ATM mode, 0 = Standard mode
Bit 10: 1 = Last operation complete, 0 = Not yet complete
FFFF
FFFD
FFFC
FFFB
FFFA
FFF9
FFF8
0 = No interrupts generated
0 = Last match unsuccessful
0 = Entry queue not empty
No error
Invalid instruction
Queue not empty for read
Table not initialized
Queue not empty for write
CAM table full
Entry queue full
PROGRAMMING MODEL
15
BIT NUMBER
MCM69C432 SCM69C432
0
ADDRESS
OFFSET
0
1
2
3
4
5
6
7
7