STK17TA8-RF25ITR Cypress Semiconductor Corp, STK17TA8-RF25ITR Datasheet - Page 21

• Manufacturer Part Number: STK17TA8-RF25ITR
• Description: IC NVSRAM 1MBIT 25NS 48SSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of STK17TA8-RF25ITR

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 001-52039 Rev. *A
Register Map Detail
M
WDF
AF
PF
OSCF
CAL
W
R
0x1FFF2
0x1FFF1
0x1FFF0
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
Match. Setting this bit to 0 causes the seconds’ value to be used in the alarm match. Setting this bit to 1 causes
the match circuit to ignore the seconds value.
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
contains the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries.
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being
reset by the user. It is cleared to 0 when the Flags register is read or on power up.
Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm registers
with the match bits = 0. It is cleared when the Flags register is read or on power up.
Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold V
to 0 when the Flags register is read or on power up.
Oscillator Fail Flag. Set to 1 on power up only if the oscillator is enabled and not running in the first 5ms of operation.
This indicates that RTC backup power failed and clock value is no longer valid. The user must reset this bit to 0
to clear this condition.
Calibration Mode. When set to 1, a 512Hz square wave is output on the INT pin. When set to 0, the INT pin resumes
normal operation. This bit defaults to 0 (disabled) on power up.
Write Enable. Setting the W bit to 1 freezes updates of the RTC registers and enables writes to RTC registers,
Alarm registers, Calibration register, Interrupt register and Flags register. Setting the W bit to 0 causes the contents
of the RTC registers to be transferred to the timekeeping counters if the time has been changed (a new base time
is loaded). This bit defaults to 0 on power up.
Read Time. Set R to 1 to captures the current time in holding registers so that clock updates are not seen during
the reading process. Set R to 0 to enable the holding register to resume clock updates. This bit defaults to 0 on
power up.
WDF
D7
D7
D7
M
(continued)
D6
D6
D6
AF
10s Centuries
10s Alarm Seconds
D5
D5
D5
PF
Real Time Clock – Centuries
OSCF
D4
D4
D4
Alarm – Seconds
Flags
Centuries
D3
D3
D3
0
CAL
D2
D2
D2
Alarm Seconds
D1
D1
D1
W
SWITCH
STK17TA8
. It is cleared
Page 21 of 24
D0
D0
D0
R
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