CY7C1568V18-375BZXC Cypress Semiconductor Corp, CY7C1568V18-375BZXC Datasheet - Page 9

• Manufacturer Part Number: CY7C1568V18-375BZXC
• Description: IC SRAM 72MBIT 375MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1568V18-375BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 375MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Echo Clocks
Echo clocks are provided on the DDR-II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free-running clocks and are
synchronized to the input clock of the DDR-II+. The timing for the
echo clocks is shown in
Valid Data Indicator (QVLD)
QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
Application Example
Figure 1
Document Number: 001-06551 Rev. *E
(CPU or ASIC)
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
MASTER
shows two DDR-II+ used in an application.
BUS
Source CLK
Source CLK
Cycle Start
Addresses
Switching Characteristics
R/W
DQ
DQ
A
SRAM#1
LD R/W
Figure 1. Application Example
on page 23.
CQ/CQ
K
ZQ
K
R = 250ohms
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. When the DLL is turned off, the device behaves in
DDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL Consid-
erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be
reset by slowing or stopping the input clocks K and K for a
minimum of 30ns. However, it is not necessary to reset the DLL
to lock to the desired frequency. During Power-up, when the
DOFF is tied HIGH, the DLL gets locked after 2048 cycles of
stable clock.
CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
DQ
A
SRAM#2
LD R/W
CQ/CQ
K
ZQ
K
R = 250ohms
Page 9 of 28
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