CY7C1568V18-375BZXC Cypress Semiconductor Corp, CY7C1568V18-375BZXC Datasheet

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... K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words (CY7C1566V18), 9-bit words (CY7C1577V18), 18-bit words (CY7C1568V18), or 36-bit words (CY7C1570V18) that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ) ...

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... Logic Block Diagram (CY7C1577V18 (21:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [0] Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Write Write Reg Reg Output Logic Control Read Data Reg Reg. Reg. 8 Reg. Write Write Reg Reg Output Logic Control Read Data Reg ...

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... Logic Block Diagram (CY7C1568V18 (20:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [1:0] Logic Block Diagram (CY7C1570V18 (19:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [3:0] Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 ...

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... Pin Configuration The pin configuration for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follow DQ4 DQ5 H DOFF V V REF DDQ DQ6 DQ7 R TDO TCK DQ4 DQ5 H DOFF V V REF DDQ DQ6 DQ7 R TDO TCK A Note 2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. ...

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... Pin Configuration (continued) The pin configuration for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follow DQ9 DQ10 DQ11 F NC DQ12 DQ13 H DOFF V V REF DDQ DQ14 L NC DQ15 DQ16 DQ17 R TDO TCK NC/144M DQ27 DQ18 DQ28 D NC DQ29 DQ19 DQ20 F NC DQ30 DQ21 ...

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... Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized arrays each for CY7C1566V18 arrays each for CY7C1577V18 arrays each 18) for CY7C1568V18, and arrays each 36) for CY7C1570V18. R/W Input Synchronous Read/Write Input ...

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... Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Pin Description output impedance are set to 0.2 x RQ, where resistor connected [x:0] that enables the minimum DDQ Page ...

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... CY7C1566V18, CY7C1577V18, and CY7C1570V18. Read Operations The CY7C1568V18 is organized internally as two arrays 18. Accesses are completed in a burst of 2 sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to the address inputs is stored in the read address register ...

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... Echo Clock1/Echo Clock1 Echo Clock2/Echo Clock2 Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 DLL These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin ...

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... Truth Table The truth table for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follows. Operation Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: (2.5 cycle Latency) Load address; wait two and half cycle; read data on consecutive K and K rising edges. ...

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... L– – Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 [3, 9] Comments [ Comments – During the data portion of a write sequence, all four bytes (D the device. L–H During the data portion of a write sequence, all four bytes (D the device. – During the data portion of a write sequence, only the lower byte (D into the device ...

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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 15 ...

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... Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. ...

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... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 10. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 [10] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- ...

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... These characteristics apply to the TAP inputs (TMS, TCK, TDI, and TDO). Parallel load levels are specified in 12. Test conditions are specified using the load in TAP AC Test Conditions. t 13. All voltage refers to ground. Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 0 Bypass Register 2 1 ...

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... Test Data In TDI Test Data Out TDO Note 14. t and t refer to the setup and hold time requirements of latching data from the boundary scan register Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Description Figure 2. TAP Timing and Test Conditions 1.8V 50Ω ...

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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Value CY7C1577V18 CY7C1568V18 000 000 00000110100 00000110100 ...

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... Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Bump ID Bit Number Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D ...

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... SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency. REF Figure 3. Power Up Waveforms > 2048 Stable Clock DDQ Stable (< + 0.1V DC per 50 ns) Fix HIGH (tie to V DDQ ) CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 . KC Var Start Normal Operation Page [+] Feedback [+] Feedback ...

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... V REF DDQ 20. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V Latch up Current..................................................... >200 mA Operating Range Range Commercial ...

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... Tested initially and after any design or process change that may affect these parameters. Parameter Description Θ Thermal Resistance JA (Junction to Ambient) Θ Thermal Resistance JC (Junction to Case) Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Test Conditions Max V , 400MHz (x8) DD Both Ports Deselected, (x9) ≥ V ≤ ...

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... Note 21. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V levels of 0.25V to 1.25V, output loading of the specified I Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Figure 4. AC Test Loads and Waveforms V = 0.75V REF V 0.75V R = 50Ω ...

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... QVLD signal. QVLD 28. Hold to >V or < Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 400 MHz Description Min Max Min Max Min Max Min Max [23] 1 – 2.50 8.40 2.66 8.40 0.4 – ...

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... Outputs are disabled (High Z) one clock cycle after a NOP. 31. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 NOP NOP NOP ...

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... CY7C1570V18-400BZXC CY7C1566V18-400BZI CY7C1577V18-400BZI CY7C1568V18-400BZI CY7C1570V18-400BZI CY7C1566V18-400BZXI CY7C1577V18-400BZXI CY7C1568V18-400BZXI CY7C1570V18-400BZXI 375 CY7C1566V18-375BZC CY7C1577V18-375BZC CY7C1568V18-375BZC CY7C1570V18-375BZC CY7C1566V18-375BZXC CY7C1577V18-375BZXC CY7C1568V18-375BZXC CY7C1570V18-375BZXC CY7C1566V18-375BZI CY7C1577V18-375BZI CY7C1568V18-375BZI CY7C1570V18-375BZI CY7C1566V18-375BZXI CY7C1577V18-375BZXI CY7C1568V18-375BZXI CY7C1570V18-375BZXI Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Package Package Type Diagram 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...

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... CY7C1566V18-300BZXI CY7C1577V18-300BZXI CY7C1568V18-300BZXI CY7C1570V18-300BZXI Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Package Package Type Diagram 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...

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... Package Diagram Document Number: 001-06551 Rev. *E CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 Figure 6. 165-Ball FBGA ( 1.4 mm) 51-85195-*A Page [+] Feedback [+] Feedback ...

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... Document History Page Document Title: CY7C1566V18/CY7C1577V18/CY7C1568V18/CY7C1570V18, 72-Mbit DDR-II+ SRAM 2-Word Burst Architec- ture (2.5 Cycle Read Latency) Document Number: 001-06551 Issue Orig. of REV. ECN No. Date Change ** 432718 See ECN NXR *A 437000 See ECN IGS *B 461934 See ECN NXR *C 497567 See ECN ...