CY7C1568V18-375BZXC Cypress Semiconductor Corp, CY7C1568V18-375BZXC Datasheet - Page 10

• Manufacturer Part Number: CY7C1568V18-375BZXC
• Description: IC SRAM 72MBIT 375MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1568V18-375BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 375MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Truth Table
The truth table for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follows.
Write Cycle Descriptions
The write cycle description table for CY7C1566V18 and CY7C1568V18 follows.
Notes
Document Number: 001-06551 Rev. *E
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
Read Cycle: (2.5 cycle Latency)
Load address; wait two and half cycle;
read data on consecutive K and K rising edges.
NOP: No Operation
Standby: Clock Stopped
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
4. Device powers up deselected with the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
8. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging
9. Is based on a write cycle is initiated per the
BWS
NWS
H
H
H
H
symmetrically.
cycle, as long as the setup and hold requirements are met.
L
L
L
L
0
0
/
BWS
NWS
H
H
H
H
L
L
L
L
1
1
/
L–H
L–H
L–H
L–H
K
–
–
–
–
Operation
L–H During the data portion of a write sequence:
L–H During the data portion of a write sequence:
L–H No data is written into the devices during this portion of a write operation.
L-H During the data portion of a write sequence:
K
–
–
–
–
During the data portion of a write sequence:
CY7C1566V18 − both nibbles (D
CY7C1568V18 − both bytes (D
CY7C1566V18 − both nibbles (D
CY7C1568V18 − both bytes (D
During the data portion of a write sequence:
CY7C1566V18 − only the lower nibble (D
CY7C1568V18 − only the lower byte (D
CY7C1566V18 − only the lower nibble (D
CY7C1568V18 − only the lower byte (D
During the data portion of a write sequence:
CY7C1566V18 − only the upper nibble (D
CY7C1568V18 − only the upper byte (D
CY7C1566V18 − only the upper nibble (D
CY7C1568V18 − only the upper byte (D
No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
table. NWS
Stopped
L-H
L-H
L-H
K
[17:0]
[17:0]
[7:0]
[7:0]
0
) are written into the device.
) are written into the device.
, NWS
) are written into the device.
) are written into the device.
[8:0]
[8:0]
[17:9]
[17:9]
LD
H
1
L
L
X
[3:0]
[3:0]
, BWS
[7:4]
[7:4]
) is written into the device, D
) is written into the device, D
Comments
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
0
, BWS
R/W
[3, 9]
H
L
X
X
CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
1
, BWS
D(A) at K(t + 1) ↑
Q(A) at K(t + 2) ↑
High Z
Previous State
2
, and BWS
[3, 4, 5, 6, 7, 8]
DQ
3
are altered on different portions of a write
[17:9]
[17:9]
[8:0]
[8:0]
[7:4]
[7:4]
[3:0]
[3:0]
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
D(A+1) at K(t + 1) ↑
Q(A+1) at K(t + 3) ↑
High Z
Previous State
Page 10 of 28
DQ
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