M25PE80-VMS6TG NUMONYX, M25PE80-VMS6TG Datasheet
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M25PE80-VMS6TG
Specifications of M25PE80-VMS6TG
Related parts for M25PE80-VMS6TG
M25PE80-VMS6TG Summary of contents
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... BP0, BP1 and BP2 bits More than 100 000 write cycles More than 20 years data retention Packages – ECOPACK® (RoHS compliant) April 2008 8-Mbit, page-erasable serial flash memory with Rev 7 M25PE80 VFQFPN8 (MP (MLP8) QFN8L (MS (MLP8) SO8W (MW) 208 mils width SO8N (MN) 150 mils width www ...
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... Active power, standby power and deep power-down modes . . . . . . . . . . 13 4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8.1 4.8.2 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Write enable (WREN 6.2 Write disable (WRDI 6.3 Read identification (RDID 2/66 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Specific hardware and software protections . . . . . . . . . . . . . . . . . . . . . 15 M25PE80 ...
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... M25PE80 6.4 Read status register (RDSR 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Write status register (WRSR 6.6 Read data bytes (READ 6.7 Read data bytes at higher speed (FAST_READ 6.8 Read lock register (RDLR 6.9 Page write (PW 6.10 Page program (PP 6.11 Write to lock register (WRLR ...
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... Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 9. Protection modes (T9HX process only Table 10. Lock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 11. Not for new design: lock registers for the M25PE80 in T7Y process . . . . . . . . . . . . . . . . . 32 Table 12. Lock register Table 13. Not for new design: lock registers for the M25PE80 in T7Y process . . . . . . . . . . . . . . . . . 38 Table 14. ...
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... M25PE80 List of figures Figure 1. Logic diagram - previous T7Y process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Logic diagram - new T9HX process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. VFQFPN, QFN8L and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8 ...
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... Description 1 Description The M25PE80 is an 8-Mbit (1 Mb ×8) serial paged flash memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. The page write instruction consists of an integrated page erase cycle followed by a page program cycle ...
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... Top sector lock or write protect Reset Supply voltage Ground Figure 1 and Figure 2). M25PE80 TSL section for package dimensions, and how to identify pin-1. Description Logic diagram - new T9HX process M25PE80 W Reset V SS Direction Input Input Output Input Input Input Input V CC Reset C D AI10780b Q AI13557 , SS 7/66 ...
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... When reset (Reset) is driven High, the memory is in the normal operating mode. When reset (Reset) is driven Low, the memory will enter the reset mode. In this mode, the output is high impedance. Driving reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost. 8/66 M25PE80 ...
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... M25PE80 2.6 Write protect (W) or top sector lock (TSL) The write protect function is available in the T9HX process only (see note on page The write protect (W) input is used to freeze the size of the area of memory that is protected against write, program and erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the status register ...
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... Resistors R (represented in that the M25PE80 is not selected if the bus master leaves the S line in the high impedance state. As the bus master may enter a state where all inputs/outputs are in high impedance at ...
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... M25PE80 Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 5. SPI modes supported CPOL CPHA µs <=> the application must ensure that the Bus p MSB SPI modes MSB AI01438B 11/66 ...
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... For optimized timings recommended to use the page write (PW) instruction to write all consecutive targeted bytes in a single sequence versus using several page write (PW) sequences with each containing only a few bytes (see Table 22: AC characteristics, and (0.11 µm) process)). 12/66 Section 6.9: Page write Table 24: AC characteristics (75 MHz operation, T9HX M25PE80 (PW), ...
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... M25PE80 4.3 A fast way to modify data The page program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. This might be: when the designer is programming the device for the first time when the designer knows that the page has already been erased by an earlier page erase (PE), subsector erase (SSE), sector erase (SE) or bulk erase (BE) instruction ...
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... Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PE80 features the following data protection mechanisms: 4.8.1 Protocol-related protections Power on reset and an internal timer (t changes while the power supply is outside the operating specification ...
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... M25PE80 4.8.2 Specific hardware and software protections The M25PE80 features a hardware protected mode, HPM, and two software protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. They are described below: HPM HPM in T7Y process (see The hardware protected mode (HPM) is entered when top sector lock (TSL) is driven Low, causing the top 256 pages of memory to become read-only ...
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... Current subsector protected from program/erase/write operations, all subsectors protection status cannot be changed except by a reset or power-up All subsectors protected with their protection status cannot be changed except by a reset or power-up. Write to lock register (WRLR) M25PE80 instruction. ...
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... M25PE80 The second software protected mode (SPM2) uses the block protect (BP2, BP1, BP0, see Section Table 4. Protected area sizes Status register content BP2 BP1 BP0 bit bit bit The device is ready to accept a bulk erase instruction if, and only if, all block protect (BP2, BP1, BP0) are 0. ...
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... CFFFFh 5 C0000h C0FFFh BF000h BFFFFh 4 B0000h B0FFFh AF000h AFFFFh 3 A0000h A0FFFh 9F000h 9FFFFh 2 90000h 90FFFh 1F000h 1FFFFh 10000h 10FFFh 0 M25PE80 Address range 143 8F000h 8FFFFh 128 80000h 80FFFh 127 7F000h 7FFFFh 112 70000h 70FFFh 111 6F000h 6FFFFh 96 60000h 60FFFh 95 5F000h 5FFFFh 80 ...
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... M25PE80 Figure 6. Block diagram Reset TSL These features (in gray) are only available in the T7Y process. Control logic I/O shift register Address register and counter F0000h 00000h 256 bytes (page size) Memory organization High voltage generator Status 256-byte register data buffer FFFFFh ...
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... That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a write cycle, program cycle or erase cycle are ignored, and the internal write cycle, program cycle or erase cycle continues unaffected. 20/66 Table 6. M25PE80 ...
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... M25PE80 Table 6. Instruction set Instruction WREN Write enable WRDI Write disable RDID Read identification RDSR Read status register WRLR Write to lock register (1) WRSR Write status register RDLR Read lock register READ Read data bytes Read data bytes at higher FAST_READ speed PW Page write ...
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... Write to lock register (WRLR) instruction completion Page erase (PE) instruction completion Sector erase (SE) instruction completion Bulk erase (BE) instruction completion. Figure 8. Write disable (WRDI) instruction sequence 22/ Instruction D High Impedance Q (Figure 8) resets the write enable latch (WEL) bit Instruction D High Impedance AI02281E AI03750D M25PE80 ...
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... M25PE80 6.3 Read identification (RDID) The Read Identification (RDID) instruction allows to read the device identification data: Manufacturer identification (1 byte) Device identification (2 bytes) A unique ID code (UID) (17 bytes, of which 16 available upon customer request) The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. ...
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... Instructions Figure 9. Read Identification (RDID) instruction sequence and data-out sequence 24/66 M25PE80 ...
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... M25PE80 6.4 Read status register (RDSR) The Read Status Register (RDSR) instruction allows the status register to be read. The status register may be read at any time, even while a program, erase or write cycle is in progress. When one of these cycles is in progress recommended to check the write in progress (WIP) bit before sending a new instruction to the device ...
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... Instructions Figure 10. Read status register (RDSR) instruction sequence and data-out sequence High Impedance Q 26/ Instruction Status Register Out MSB Status Register Out MSB M25PE80 0 7 AI02031E ...
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... The write status register (WRSR) instruction allows new values to be written to the status register. Note: The status register BPi and SRWD bits are available in the M25PE80 in the T9HX process only. See Important note on page 6 Before the write status register (WRSR) instruction can be accepted, a write enable (WREN) instruction must previously have been executed ...
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... BP2, BP1 and BP0 bits can be changed Status register is hardware write protected The values in the SRWD, (HPM) BP2, BP1 and BP0 bits cannot be changed 6. M25PE80 (1) ) Memory content (2) Protected area Unprotected area Protected against Ready to accept page program, page program and ...
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... M25PE80 6.6 Read data bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that ...
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... Figure 13. Read data bytes at higher speed (FAST_READ) instruction sequence and data-out sequence High Impedance Address bits A23 to A20 are don’t care. 30/66 , during the falling edge of Serial Clock (C). C Figure 13 Instruction 24-bit address Dummy byte DATA OUT MSB DATA OUT MSB M25PE80 0 7 MSB AI04006 ...
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... M25PE80 6.8 Read lock register (RDLR) The device is first selected by driving Chip Select (S) Low. The instruction code for the read lock register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any location inside the concerned sector (or subsector). Each address bit is latched-in during the rising edge of Serial Clock (C) ...
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... Instructions Table 11. Not for new design: lock registers for the M25PE80 in T7Y process Bit Bit name b7-b4 Subsector lock b3 down Subsector write b2 (2) lock b1 Sector lock down b0 Sector write lock 1. See: Important note on page 2. Valid only for sector 0 and sector 15 (the value ‘0’ is returned for other sectors). ...
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... M25PE80 6.9 Page write (PW) The page write (PW) instruction allows bytes to be written in the memory. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL) ...
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... Instructions Figure 15. Page write (PW) instruction sequence MSB 1. Address bits A23 to A20 are don’t care ≤ n ≤ 256. 34/ Instruction 24-bit address MSB Data byte 2 Data byte MSB Data byte MSB Data byte MSB M25PE80 AI04045 ...
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... M25PE80 6.10 Page program (PP) The page program (PP) instruction allows bytes to be programmed in the memory (changing bits from only). Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). ...
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... Instructions Figure 16. Page program (PP) instruction sequence MSB 1. Address bits A23 to A20 are don’t care ≤ n ≤ 256. 36/ Instruction 24-bit address MSB Data byte 2 Data byte MSB Data byte MSB Data byte MSB M25PE80 AI04044 ...
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... M25PE80 6.11 Write to lock register (WRLR) The write to lock register (WRLR) instruction allows bits to be changed in the lock registers. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL) ...
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... Instructions Table 13. Not for new design: lock registers for the M25PE80 in T7Y process Sector All sectors in T9HX process All sectors except for sector 0 and sector 15 in T7Y process Sector 0, sector 15 in T7Y process 1. The table rows in gray are true for products processed in the T7Y process only. ...
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... M25PE80 1. the sector WL bit is first set to ‘0’ (and all subsectors that are not locked-down will have their WL bit reset to ‘0’). 2. the sector LD bit and all subsectors LD bits are set to ‘1’. In this case, the final value of the above subsector lock register is xxxx1010b. ...
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... D 1. Address bits A23 to A20 are don’t care. 40/66 Figure 18. pulse). On Reset going Low, the device enters the reset mode and see Table 26: Timings after a Reset Low pulse RHSL Instruction 24-bit address 23 22 MSB M25PE80 ) is initiated. PE Table 15: Device in Section 11 AI04046 ...
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... M25PE80 6.13 Subsector erase (SSE) Note: The subsector erase (SSE) instruction is decoded only in the M25PE80 in the T9HX process (see Important note on page The subsector erase (SSE) instruction sets to ‘1’ (FFh) all bits inside the chosen subsector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed ...
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... D 1. Address bits A23 to A20 are don’t care. 42/ valid address for the sector erase (SE) instruction. Chip Select (S) Figure 20. see Table 26: Timings after a Reset Low pulse Instruction 23 22 MSB SE Table 15: Device status after a in Section 11: DC and 24-bit address AI03751D M25PE80 ) is ...
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... M25PE80 6.15 Bulk erase (BE) The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). ...
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... Any deep power-down (DP) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 22. Deep power-down (DP) instruction sequence 44/66 Figure 22 Instruction M25PE80 specified CC1 CC2 before the supply current is reduced Standby mode Deep power-down mode AI03753D ...
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... M25PE80 6.17 Release from deep power-down (RDP) Once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down (RDP) instruction. Executing this instruction takes the device out of the deep power-down mode. The release from deep power-down (RDP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on serial data input (D) ...
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... PUW rail decoupled by a suitable capacitor close to CC drops from the operating voltage, to below the power on reset CC , all operations are disabled and the device does not respond WI VSL modes. is less than the CC rises above CC (min), the device can M25PE80 supply. ...
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... M25PE80 Figure 24. Power-up timing (max (min) Reset state of the device V WI Table 14. Power-up timing and V Symbol ( (min low VSL CC (1) t Time delay before the first write, program or erase instruction PUW (1) V Write inhibit voltage WI 1. These parameters are characterized only, over the temperature range –40 °C to +85 °C. ...
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... Device deselected (S High) and in standby mode 1. S remains Low while Reset is Low. 48/66 Lock bits status (1) : WREN, Reset to 0 Reset to 0 Reset to 0 Reset to 0 M25PE80 Internal logic Addressed data status Same as POR Not significant Equivalent to Addressed data POR could be modified Equivalent to Write is correctly ...
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... M25PE80 9 Initial delivery state The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte contains FFh). All usable status register bits are 0. 10 Maximum rating Stressing the device above the rating listed in the cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... CC 0.2V CC Parameter Test condition V OUT V IN =25 °C and a frequency of 33 MHz. A Min Max 2.7 3.6 –40 85 Min Max 30 5 0. 0. Input and output timing reference levels 0.7V CC 0.3V CC AI00825B Min Max = M25PE80 Unit V °C Unit Unit pF pF ...
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... M25PE80 Table 20. DC characteristics Symbol I Input leakage current LI I Output leakage current LO Standby current I CC1 (standby and reset modes) I Deep power-down current CC2 Operating current I CC3 (FAST_READ) I Operating current (PW) CC4 I Operating current (SE) CC5 V Input low voltage IL V Input high voltage IH V Output low voltage ...
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... Page write cycle time (256 bytes) Page write cycle time (n bytes) Page program cycle time (256 bytes) Page program cycle time (n bytes) Page erase cycle time Sector erase cycle time Bulk erase cycle time . C M25PE80 and Table 18 Min Typ Max Unit D.C. 50 MHz D ...
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... M25PE80 Table 23. AC characteristics (50 MHz operation, Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, RDLR, PW, PP, WRLR, PE, SE SSE, DP, RDP, WREN, WRDI, RDSR, WRSR f Clock frequency for read instructions R ( Clock high time CH CLH ( Clock low time CL CLL ...
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... A. For instance, int(12/ int(32/ int(15.3) =16. 54/66 Table 17 Parameter (2) (peak to peak (1) ) µm) process and Table 18 Min Typ Max D. 100 8 8 100 0.8 3 (6) int(n/8) × 0.025 150 10 20 M25PE80 Unit MHz MHz µs µ ...
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... M25PE80 Figure 26. Serial input timing S tCHSL C tDVCH D Q Figure 27. Top sector lock (T7Y process) or write protect (T9HX process) setup and hold timing TSL or W tTHSL tWHSL High Impedance Q 1. For the differences between devices produced in the two processes, see tSLCH tCHDX ...
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... DC and AC parameters Figure 28. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D 56/66 tCH tCLQV tQLQH tQHQL M25PE80 tCL tSHQZ LSB OUT AI01449e ...
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... M25PE80 Table 25. Reset conditions Symbol Alt. ( RLRH RST t SHRH 1. Value guaranteed by characterization, not 100% tested in production. Table 26. Timings after a Reset Low pulse Symb Alt. Parameter ol Reset t t recovery RHSL REC time 1. All the values are guaranteed by characterization, and not 100% tested in production. ...
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... JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 30. VFQFPN8 (MLP8) 8-lead very thin dual flat package no lead, 6 × 5 mm, package outline Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. 58/ aaa 0. 0. ddd C 70-ME M25PE80 ...
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... M25PE80 Table 27. VFQFPN8 (MLP8) 8-lead very thin dual flat package no lead, 6 × 5 mm, package mechanical data Symbol Θ aaa bbb ddd millimeters Typ Min Max 0.85 0.80 1.00 0.00 0.05 0.65 0.20 0.40 0.35 0.48 6.00 5.75 3.40 3.20 3.60 5.00 4 ...
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... ID OPTION 0.08 inches Typ Min 0.035 0.031 0.001 0.000 0.008 0.016 0.014 0.236 0.118 0.110 0.197 0.118 0.110 0.050 0.024 0.020 M25PE80 5X_ME Max 0.039 0.002 0.019 0.126 0.126 0.030 ...
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... M25PE80 Figure 32. SO8 wide – 8 lead plastic small outline, 208 mils body width, package outline 1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 29. SO8 wide – 8 lead plastic small outline, 208 mils body width, mechanical ...
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... GAUGE PLANE SO-A inches Typ Min 0.004 0.049 0.011 0.007 0.193 0.189 0.236 0.228 0.154 0.150 0.050 – 0.010 0° 0.016 0.041 M25PE80 Max 0.069 0.010 0.019 0.009 0.004 0.197 0.244 0.157 – 0.020 8° 0.050 ...
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... Exposed pad mm. Note: For a list of available options (speed, package, etc.), for further information on any aspect of this device or when ordering parts operating at 75 MHz (0.11 µm, process digit ‘4’), please contact your nearest Numonyx sales office. M25PE80 (1) (2) Ordering information – ...
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... PP modified in Table 20: DC CC3 and t modified in Table 22 Plating technology, blank option removed. Figure 6: Block and Figure 32. Note 1 (below Figure 12), (below Figure 15), Note 1 (below Note 1 (below Figure 20). M25PE80 scheme. data, Page , PW diagram. Note 1 Figure 16), ...
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... T added and V max changed in LEAD IO ratings M25PE80 products processed in T9HX process added to datasheet: – WP pin replaces TSL (T7Y technology), see (W) or top sector lock (TSL) – Write status register (WRSR) added for T9HX process – subsector protection granularity removed in T9HX process, still exists in T7Y process – ...
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... Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 66/66 Please Read Carefully: applications. visiting Numonyx's website at http://www.numonyx.com. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. M25PE80 ...