NAND01GW4B2AN6E STMicroelectronics, NAND01GW4B2AN6E Datasheet - Page 19

• Manufacturer Part Number: NAND01GW4B2AN6E
• Description: IC FLASH 1GBIT 48TSOP
• Manufacturer: STMicroelectronics

Specifications of NAND01GW4B2AN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 1G (64M x 16)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

NAND01G-B, NAND02G-B
3.12
4
4.1
4.2
4.3
V
Ground, V
ground.
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see
Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
Command Input
Command Input bus operations are used to give commands to the memory. Commands are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See
Address Input
Address Input bus operations are used to input the memory addresses. Four bus cycles are
required to input the addresses for 1Gb devices whereas five bus cycles are required for the
2Gb device (refer to
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See
Data Input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See
SS
Figure 23
Figure 24
Figure 25
Ground
SS,
is the reference for the power supply. It must be connected to the system
and
and
and
Table 5: Bus
Table 24
Table 24
Table 24
Table 6
for details of the timings requirements.
and
for details of the timings requirements.
and
Operations, for a summary.
Table
Table 25
7, Address Insertion).
for details of the timings requirements.
Bus operations
19/64