M95128-WMN6P STMicroelectronics, M95128-WMN6P Datasheet - Page 18

• Manufacturer Part Number: M95128-WMN6P
• Description: IC EEPROM 128KBIT 5MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M95128-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 128K (16K x 8)
• Speed: 5MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 16 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 5 MHz
• Access Time: 60 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 6.5 V
• Memory Configuration: 16384 X 8
• Clock Frequency: 10MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8607-5; M95128-WMN6P

Instructions
5.4
18/44
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
sending the instruction code followed by the data byte on Serial Data input (D), and driving
the Chip Select (S) signal high. Chip Select (S) must be driven high after the rising edge of
Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not
executed.
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed write cycle that takes t
Table
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write
cycle t
reset at the end of the write cycle t
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 and SRWD bits:
●
●
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0
bits in the Status Register. Bits b6, b5, b4 are always read as 0.
Table 5.
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in
signal
W
1
0
1
0
The Block protect (BP1, BP0) bits define the size of the area that is to be treated as
read only, as defined in
The SRWD bit (Status register write disable bit), in accordance with the signal read on
the Write protect pin (W), allows the user to set or reset the write protection mode of the
Status Register itself, as shown in
Write Status Register (WRSR) instruction is not executed.
19). The instruction sequence is shown in
W
, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also
SRWD
bit
0
0
1
1
Protection modes
Hardware
Protected
Protected
Software
(SPM)
(HPM)
Mode
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
The values in the BP1
and BP0 bits can be
changed
Status Register is
Hardware write protected
The values in the BP1
and BP0 bits cannot be
changed
W
Table
Write protection of the
Doc ID 5798 Rev 13
to complete (as specified in
Status Register
W
W
5.
write cycle.
.
Table
5. When in the Write-protected mode, the
Figure
Write Protected
Write Protected
Protected area
8.
Table
M95128, M95128-W, M95128-R
Memory content
16,
(1)
Table
Ready to accept Write
instructions
Ready to accept Write
instructions
Unprotected area
17,
Table 19
Table
5.
and
(1)