M95128-W STMICROELECTRONICS [STMicroelectronics], M95128-W Datasheet
M95128-W
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M95128-W Summary of contents
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... Features Compatible with SPI bus serial interface (positive clock SPI modes) Single supply voltage: – 4.5 to 5.5 V for M95128 – 2.5 to 5.5 V for M95128-W – 1.8 to 5.5 V for M95128-R High speed – 5 MHz clock rate write time Status Register Hardware protection of the Status Register ...
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... CC Operating supply voltage Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 M95128, M95128-W, M95128-R ...
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... M95128, M95128-W, M95128-R 5.6.1 6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ECC (error correction code) and Write cycling . . . . . . . . . . . . . . . . . . . 23 Contents 3/44 ...
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... DC characteristics (M95128- Table 16. AC characteristics (M95128, device grade Table 17. AC characteristics (M95128-W, device grade Table 18. AC characteristics (M95128-W, device grade Table 19. AC characteristics (M95128-R Table 20. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 21. TSSOP8 – ...
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... M95128, M95128-W, M95128-R List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO, UFDFPN and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9 ...
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... Description 1 Description The M95128, M95128-W and M95128-R are electrically erasable programmable memory (EEPROM) devices accessed by a high speed SPI-compatible bus. The memory array is organized as 16384 x 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in The device is selected when Chip Select (S) is taken Low ...
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... M95128, M95128-W, M95128-R Table 1. Signal names Signal name HOLD Function Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply voltage Ground Description Direction Input Input Output Input Input Input 7/44 ...
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... Memory organization 2 Memory organization The memory is organized as shown in Figure 3. Block diagram HOLD W Control Logic Address Register 8/44 Figure 3. I/O Shift Register and Counter M95128, M95128-W, M95128-R High Voltage Generator Data Register Status Register 1 Page X Decoder Size of the Read only EEPROM area AI01272C ...
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... M95128, M95128-W, M95128-R 3 Signal description See Figure 1: Logic diagram connected to this device. 3.1 Serial Data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 3.2 Serial Data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written ...
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... CC CC (min), V (max)] range must be applied (see CC CC continuously rises from has reached the power on reset threshold voltage (this threshold is CC operating voltage defined in CC M95128, M95128-W, M95128-R voltage CC Table 7, Table During this SS CC voltage via a suitable pull-up resistor. ...
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... M95128, M95128-W, M95128-R 3.7.4 Power-down At power-down (continuous decrease in V operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During power-down, the device must be deselected (the Chip Select (S) should be allowed to follow the voltage applied on V Power mode (that is there should be no internal Write cycle in progress). ...
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... The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 4 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being Low. Figure 4. Hold condition activation C HOLD 12/44 M95128, M95128-W, M95128-R Figure 4). Hold Condition Hold Condition AI02029D ...
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... SPI bus. Table 2. Write-protected block size Status Register bits BP1 (RDSR). Protected block BP0 0 none 1 Upper quarter 0 Upper half 1 Whole memory Operating features Array addresses protected M95128, M95128-W, M95128-R none 3000h - 3FFFh 2000h - 3FFFh 0000h - 3FFFh 13/44 ...
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... Write to Memory Array 5, to send this instruction to the device, Chip Select (S) is driven Low Instruction D High Impedance Q M95128, M95128-W, M95128-R Table 3. Table 3), the device automatically Instruction format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 5 ...
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... M95128, M95128-W, M95128-R 5.2 Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High ...
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... Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4. Status Register format b7 SRWD Status Register Write Protect 16/44 Table 4) becomes protected against Write M95128, M95128-W, M95128-R Figure 7. BP1 BP0 WEL Block Protect bits Write Enable Latch bit Write In Progress bit b0 WIP ...
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... M95128, M95128-W, M95128-R Figure 7. Read Status Register (RDSR) sequence High Impedance Instruction Status Register Out MSB Instructions Status Register Out MSB 7 AI02031E 17/44 ...
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... The contents of the SRWD and BP1, BP0 bits are updated after the completion of the Write Status Register (WRSR) instruction, including the t 18/44 and Table 19), at the end of which the Write in Progress (WIP) bit is reset Figure 4. M95128, M95128-W, M95128-R (as specified and is 0 when it is completed. When the W Table 5), mode in which the Write Write cycle ...
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... M95128, M95128-W, M95128-R Table 5. Protection modes SRWD W signal bit defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial ...
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... Instructions Figure 8. Write Status Register (WRSR) sequence 20/ Instruction Register High Impedance MSB M95128, M95128-W, M95128-R Status AI02282D ...
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... M95128, M95128-W, M95128-R 5.5 Read from Memory Array (READ) As shown in Figure Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). ...
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... Chip Select (S) is driven high after the eighth bit of the data byte Instruction 16-Bit Address High Impedance M95128, M95128-W, M95128-R (as specified in Table 16 to Table Figure 11., the next byte Data Byte ...
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... M95128, M95128-W, M95128-R Figure 11. Page Write (WRITE) sequence The most significant address bits (b15, b14) are Don’t Care. 5.6.1 ECC (error correction code) and Write cycling The M95128 devices offer an ECC (error correction code) logic which compares each 4-byte word with 6 EEPROM bits of ECC ...
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... S line in the high impedance state. 24/44 R SDO SDI SCK SPI memory R R device S HOLD W Figure 12) ensures that a device is not selected if the M95128, M95128-W, M95128 SPI memory SPI memory R device device S S HOLD ...
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... M95128, M95128-W, M95128-R In applications where the bus master might enter a state where all inputs/outputs SPI bus would be in high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pull- ...
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... Output voltage O V Input voltage I V Supply voltage CC V Electrostatic discharge voltage (human body model) ESD 1. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500W, R2=500 ). 26/44 M95128, M95128-W, M95128-R Table 6 may cause permanent damage to Parameter (1) Min. Max. Unit –40 130 °C –65 150 ° ...
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... Table 7. Operating conditions (M95128) Symbol V Supply voltage CC T Ambient operating temperature (device grade 3) A Table 8. Operating conditions (M95128-W) Symbol V Supply voltage CC Ambient operating temperature (device grade Ambient operating temperature (device grade 3) Table 9. Operating conditions (M95128-R) ...
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... Sampled only, not 100% tested 28/44 (1) Parameter Input Levels Timing Reference Levels 0.8V CC 0.2V CC (1) Parameter Test condition V OUT =25 °C and a frequency of 5 MHz. A M95128, M95128-W, M95128-R Min. Max. 100 50 0. 0. Input and Output 0.7V CC 0.3V CC AI00825B Min. Max ...
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... V Output low voltage OL (1) V Output high voltage OH 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards. Table 13. DC characteristics (M95128-W, device grade 6) Symbol I Input leakage current LI I Output leakage current LO I Supply current (Read) ...
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... DC and AC parameters Table 14. DC characteristics (M95128-W, device grade 3) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current (Read) CC (1) I Supply current (Write) CC0 Supply current I CC1 (Standby Power mode) V Input low voltage IL V Input high voltage IH V Output low voltage ...
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... M95128, M95128-W, M95128-R Table 16. AC characteristics (M95128, device grade 3) Test conditions specified in Symbol Alt Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 deselect time SHSL active hold time CHSH ...
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... DC and AC parameters Table 17. AC characteristics (M95128-W, device grade 6) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH ...
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... M95128, M95128-W, M95128-R Table 18. AC characteristics (M95128-W, device grade 3) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX ...
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... Clock low setup time before HOLD not active Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time M95128, M95128-W, M95128-R and Table 9 (1) (1) Min. Max. Unit D.C. ...
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... M95128, M95128-W, M95128-R Figure 15. Serial input timing S tCHSL C tDVCH D Q Figure 16. Hold timing HOLD tSLCH tCHDX MSB IN High Impedance tHLCH tCLHL tHLQZ DC and AC parameters tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN AI01447C tHHCH tCLHH tHHQV AI01448B 35/44 ...
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... DC and AC parameters Figure 17. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D 36/44 tCH tCLQV tQLQH tQHQL M95128, M95128-W, M95128-R tCL tSHQZ LSB OUT AI01449e ...
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... M95128, M95128-W, M95128-R 10 Package mechanical Figure 18. SO8N – 8 lead plastic small outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 20. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data Symbol ccc ...
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... M95128, M95128-W, M95128 TSSOP8AM (1) inches Typ Min Max 0.0472 0.0020 0.0059 0.0394 0.0315 0.0413 0.0075 0.0118 0.0035 0.0079 0.0039 ...
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... M95128, M95128-W, M95128-R Figure 20. UFDFPN8, 8-lead ultra thin fine pitch dual flat package no lead mm, outline 1. Not to scale. Table 22. UFDFPN8, 8-lead ultra thin fine pitch dual flat package no lead mm, mechanical data Symbol (2) ddd 1 ...
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... ST sales office. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 40/44 M95128, M95128-W, M95128-R M95128 – (1) ...
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... M95128, M95128-W, M95128-R Table 24. Available M95128x products (package, voltage range, temperature grade) Package DIP8 (BN) SO8N (MN) MLP8 (MB) TSSOP (DW) M95128-R M95128-W (1 5 Range 6 Range 6 Range 6/Range 3 Range 6 Range 6 Range 6 Range 6/Range 3 Part numbering M95128 (4 5.5 V) Range 3 Range 3 41/44 ...
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... RoHS compliant devices. Device grade information clarified M95128 datasheet merged back in. Product List summary table added. 5.0 AEC-Q100-002 compliance. Device Grade information clarified. tHHQX corrected to tHHQV. 10MHz product becomes standard M95128, M95128-W, M95128-R Changes (min) and V (min) changed. Soldering IO CC ...
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... Table 19: AC characteristics T added to Table 6: Absolute maximum A PDIP8 (BN) and SO8 wide (MW) packages removed. M95128-W and M95128-R are no longer under development. Test conditions changed for V characteristics (M95128-W, device grade Figure 12: Bus master and memory devices on the SPI bus SO8N package specifications updated (see ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 44/44 Please Read Carefully: © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com M95128, M95128-W, M95128-R ...