M29DW640F70N6E NUMONYX, M29DW640F70N6E Datasheet
M29DW640F70N6E
Specifications of M29DW640F70N6E
Available stocks
Related parts for M29DW640F70N6E
M29DW640F70N6E Summary of contents
Page 1
... Random Access 60, 70ns Programming time – 10µs per Byte/Word typical – 4 Words / 8 Bytes at-a-time Program Memory blocks – Quadruple Bank Memory Array: 8Mbit+24Mbit+24Mbit+8Mbit – Parameter Blocks (at both Top and Bottom) Dual operations – While Program or Erase in a group of banks (from 1 to 3), Read in any of the ...
Page 2
Contents Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
M29DW640F 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 4.2 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
... Contents Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Appendix B Common Flash Interface (CFI Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 C.1 Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 C.2 Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Appendix D Block protection D.1 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 D.2 In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4/74 M29DW640F ...
Page 5
M29DW640F List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
List of figures List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
... The bank architecture is summarized in of the Parameter Blocks are at the top of the memory address space, and eight are at the bottom. The M29DW640F has one extra 256 Byte block (Extended Block) that can be accessed using a dedicated command ...
Page 8
Summary description Figure 1. Logic diagram Table 1. Signal names A0-A21 DQ0-DQ7 DQ8-DQ14 DQ15A– BYTE / 8/ / A0-A21 W M29DW640F E ...
Page 9
M29DW640F Figure 2. TSOP connections A15 1 A14 A13 A12 A11 A10 A9 A8 A19 A20 M29DW640F A21 /WP RB A18 A17 Summary description 48 A16 ...
Page 10
Summary description Figure 3. TFBGA48 connections (top view through package Balls are shorted together via the substrate but not connected to the die. Table 2. Bank architecture Bank Bank Size A ...
Page 11
M29DW640F Figure 4. Block addresses (x8) 000000h 8 KByte or 4 KWord 001FFFh 00E000h 8 KByte or 4 KWord 00FFFFh Bank A 010000h 64 KByte or 32 KWord 01FFFFh 0F0000h 64 KByte or 32 KWord 0FFFFFh 100000h 64 KByte or ...
Page 12
Summary description Figure 5. Block addresses (x16) 000000h 8 KByte or 4 KWord 000FFFh 007000h 8 KByte or 4 KWord 007FFFh Bank A 008000h 64 KByte or 32 KWord 00FFFFh 078000h 64 KByte or 32 KWord 07FFFFh 080000h 64 KByte ...
Page 13
... Figure 1: Logic connected to this device. 2.1 Address Inputs (A0-A21) The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. 2.2 Data Inputs/Outputs (DQ0-DQ7) The Data I/O outputs the data stored at the selected address during a Bus Read operation ...
Page 14
... Signal descriptions 2.7 Write Enable (W) The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. 2.8 V /Write Protect (V PP The V /Write Protect pin provides two functions. The V PP use an external high voltage power supply to reduce the time required for Program operations ...
Page 15
... This prevents Bus Write operations from accidentally damaging the data LKO during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the V Ground pin to decouple the current surges from the power supply ...
Page 16
Signal descriptions 2.13 V Ground the reference for all voltage measurements. The device features two V SS which must be connected to the system ground. 16/74 M29DW640F pins both of SS ...
Page 17
... Write operations are only allowed in one bank at a time. See Table 4 and on Chip Enable, Write Enable, and Reset pins are ignored by the memory and do not affect bus operations. 3.1 Bus Read Bus Read operations read from the memory cells, or specific registers in the Command Interface ...
Page 18
... They require V applied to some pins. 3.6.1 Electronic Signature The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in and Table 5, Bus operations ...
Page 19
M29DW640F Table 4. Bus operations, BYTE = V Operation E G Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read ...
Page 20
Bus operations Table 5. Bus operations, BYTE = V Operation E G Bus Read Bus Write Output Disable Standby Read Manufacturer Code ...
Page 21
... The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. If the Read/Reset command is issued during the timeout of a Block erase operation then the memory will take up to 10µs to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend ...
Page 22
... When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. 22/ and A1 and A21-A19 set to Bank Address A ...
Page 23
... Table 8 for value) of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued ...
Page 24
Command interface It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command ...
Page 25
... Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 4.2 ...
Page 26
Command interface 4.2.2 Quadruple Word Program command This is used to write a page of four adjacent Words, in x16 mode, in parallel. The addresses of the four Words must differ only in A1 and A0. Five bus write cycles ...
Page 27
... Read mode. Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. ...
Page 28
... Unlock Bypass Program command The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller ...
Page 29
M29DW640F 4.3.3 Block Protect and Chip Unprotect commands Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are shown in Appendix A, Table 24: Block inside the blocks to be changed. Block Protect and Chip ...
Page 30
Command interface Table 7. Commands, 8-bit mode, BYTE = V 1st 2nd Command Read/Reset 3 AAA AA 555 55 Auto Select 3 AAA AA 555 55 Program 4 AAA AA 555 55 AAA Double ...
Page 31
M29DW640F Table 8. Program, Erase times and Program, Erase Endurance cycles Parameter Chip Erase Block Erase (64 KBytes) Erase Suspend latency time Byte Program ( at-a-time) Word Program ( at-a-time) Chip Program (Byte ...
Page 32
... DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’ ...
Page 33
... Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’ ...
Page 34
Status register Table 9. Status Register Bits Operation Address Program Bank address Program During Erase Bank address Suspend Program Error Bank address Chip Erase Any address Erasing block Block Erase before timeout Non-Erasing block Erasing block Block Erase Non-Erasing block ...
Page 35
M29DW640F Figure 7. Toggle flowchart Address of Bank being Programmed or Erased. START READ DQ6 ADDRESS = BA READ DQ5 & DQ6 ADDRESS = BA DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 ...
Page 36
... The Multiple Bank Architecture of the M29DW640F gives greater flexibility for software developers to split the code and data spaces within the memory array. The Dual Operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased ...
Page 37
M29DW640F Table 11. Dual operations allowed in same bank Status of bank Read Read Status Array Idle Yes Programming No Erasing No Program (6) Yes Suspended (6) Erase Suspended Yes 1. Read Status Register is not a command. The Status ...
Page 38
Maximum ratings 7 Maximum ratings Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are ...
Page 39
M29DW640F 8 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the ...
Page 40
DC and AC parameters Figure 9. AC measurement Load Circuit V PP Table 14. Device capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. 40/ DEVICE UNDER TEST 0.1µF 0.1µF ...
Page 41
M29DW640F Table 15. DC characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO (1) I Supply Current (Read) CC1 I Supply Current (Standby) CC2 Supply Current (1)(2) I CC3 (Program/Erase) V Input Low voltage IL V ...
Page 42
DC and AC parameters Figure 10. Random Read AC waveforms A0-A21/ A– DQ0-DQ7/ DQ8-DQ15 BYTE tELBL/tELBH 42/74 tAVAV VALID tAVQV tELQV tELQX tGLQX tGLQV tBHQV tBLQZ M29DW640F tAXQX tEHQX tEHQZ tGHQX tGHQZ VALID AI05559 ...
Page 43
M29DW640F Figure 11. Page Read AC waveforms DC and AC parameters 43/74 ...
Page 44
DC and AC parameters Table 16. Read AC characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ACC t t Address Valid to Output Valid (Page) AVQV1 PAGE ...
Page 45
M29DW640F Figure 12. Write AC waveforms, Write Enable controlled A0-A21/ A– DQ0-DQ7/ DQ8-DQ15 V CC tVCHEL RB tAVAV VALID tAVWL tELWL tGHWL tWLWH tDVWH DC and AC parameters tWLAX tWHEH tWHGL tWHWL tWHDX VALID tWHRL AI05560 45/74 ...
Page 46
DC and AC parameters Table 17. Write AC characteristics, Write Enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Write Enable Low AVWL Input Valid to Write ...
Page 47
M29DW640F Figure 13. Write AC waveforms, Chip Enable controlled A0-A21/ A– DQ0-DQ7/ DQ8-DQ15 V CC tVCHWL RB tAVAV VALID tAVEL tWLEL tGHEL tELEH tDVEH DC and AC parameters tELAX tEHWH tEHGL tEHEL tEHDX VALID tEHRL AI05561 47/74 ...
Page 48
DC and AC parameters Table 18. Write AC characteristics, Chip Enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Chip Enable Low AVEL Input Valid to Chip ...
Page 49
M29DW640F Figure 14. Toggle and Alternative Toggle Bits mechanism, Chip Enable controlled Address Outside the Bank A0-A21 Being Programmed or Erased A Data (1) (2) DQ2 /DQ6 Read Operation outside the Bank Being Programmed or Erased 1. The ...
Page 50
DC and AC parameters Table 19. Toggle and Alternative Toggle Bits AC characteristics Symbol Alt t Address Transition to Chip Enable Low AXEL t Address Transition to Output Enable Low AXGL Figure 16. Reset/Block Temporary Unprotect AC waveforms W, E, ...
Page 51
M29DW640F Table 20. Reset/Block Temporary Unprotect AC characteristics Symbol Alt (1) t PHWL RP High to Write Enable Low, Chip Enable t t PHEL RH Low, Output Enable Low (1) t PHGL (1) t RHWL RB High to Write Enable ...
Page 52
Package mechanical 9 Package mechanical Figure 18. TSOP48 – 48 lead Plastic Thin Small Outline 20mm, package outline DIE 1. Drawing is not to scale. Table 21. TSOP48 – 48 lead Plastic Thin Small Outline, ...
Page 53
M29DW640F Figure 19. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline FE BALL "A1" Drawing is not to scale. Table 22. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data Symbol ...
Page 54
... This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest ST sales office. Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office ...
Page 55
M29DW640F Appendix A Block addresses Table 24. Block addresses (KBytes/ Block KWords) 0 8/4 1 8/4 2 8/4 3 8/4 4 8/4 5 8/4 6 8/4 7 8/4 8 64/32 9 64/32 10 64/32 11 64/32 12 64/32 13 64/32 ...
Page 56
Block addresses Table 24. Block addresses (continued) (KBytes/ Block KWords) 23 64/32 24 64/32 25 64/32 26 64/32 27 64/32 28 64/32 29 64/32 30 64/32 31 64/32 32 64/32 33 64/32 34 64/32 35 64/32 36 64/32 37 64/32 ...
Page 57
M29DW640F Table 24. Block addresses (continued) (KBytes/ Block KWords) 55 64/32 56 64/32 57 64/32 58 64/32 59 64/32 60 64/32 61 64/32 62 64/32 63 64/32 64 64/32 65 64/32 66 64/32 67 64/32 68 64/32 69 64/32 70 ...
Page 58
Block addresses Table 24. Block addresses (continued) (KBytes/ Block KWords) 87 64/32 88 64/32 89 64/32 90 64/32 91 64/32 92 64/32 93 64/32 94 64/32 95 64/32 96 64/32 97 64/32 98 64/32 99 64/32 100 64/32 101 64/32 ...
Page 59
M29DW640F Table 24. Block addresses (continued) (KBytes/ Block KWords) 119 64/32 120 64/32 121 64/32 122 64/32 123 64/32 124 64/32 125 64/32 126 64/32 127 64/32 128 64/32 129 64/32 130 64/32 131 64/32 132 64/32 133 64/32 134 ...
Page 60
... Common Flash Interface (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary ...
Page 61
M29DW640F Table 27. CFI Query System Interface Information Address Data x16 x8 1Bh 36h 0027h 1Ch 38h 0036h 1Dh 3Ah 00B5h 1Eh 3Ch 00C5h 1Fh 3Eh 0004h 20h 40h 0000h 21h 42h 000Ah 22h 44h 0000h 23h 46h 0004h 24h ...
Page 62
Common Flash Interface (CFI) Table 28. Device Geometry Definition Address Data x16 x8 27h 4Eh 0017h 28h 50h 0002h 29h 52h 0000h 2Ah 54h 0003h 2Bh 56h 0000h 2Ch 58h 0003h 2Dh 5Ah 0007h 2Eh 5Ch 0000h 2Fh 5Eh 0020h ...
Page 63
M29DW640F Table 29. Primary Algorithm-specific Extended Query table Address Data x16 x8 40h 80h 0050h 41h 82h 0052h 42h 84h 0049h 43h 86h 0031h 44h 88h 0033h 45h 8Ah 0000h 46h 8Ch 0002h 47h 8Eh 0001h 48h 90h 0001h 49h ...
Page 64
Common Flash Interface (CFI) Table 29. Primary Algorithm-specific Extended Query table Address Data x16 x8 58h B0h 0017h 59h B2h 0030h 5Ah B4h 0030h 5Bh B6h 0017h Table 30. Security Code Area Address x16 x8 61h C3h, C2h XXXX 62h ...
Page 65
... Section 4.3.2: Exit Extended Block and Table 7: Commands, 8-bit mode, BYTE = Table 31: Extended Block address and flowchart, for a detailed explanation of the technique). Appendix and Figure 21: Programmer Equipment Chip Extended Memory Block Table 4: Bus VIH, respectively, for details of Section 4.3: Block command, and to Table 6: VIL ...
Page 66
... Extended Memory Block Once the Extended Block is programmed and protected, the Exit Extended Block command must be issued to exit the Extended Block mode and return the device to Read mode. Table 31. Extended Block address and data Address Device x8 000000h-00000Fh 000010h-00007Fh 000080h-0000FFh 1. See Table 24: Block addresses ...
Page 67
... Appendix D Block protection Block protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to Protection Groups. Once protected, Program and Erase operations within the protected group fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP ...
Page 68
Block protection Note: RP can be either at V Extended Block. Table 32. Programmer technique bus operations, BYTE = V Operation E G Block (Group ( Protect Chip Unprotect Block (Group) V ...
Page 69
M29DW640F Figure 20. Programmer Equipment Group Protect flowchart 1. Block Protection Groups are shown in START ADDRESS = GROUP ADDRESS Wait 4µs W ...
Page 70
Block protection Figure 21. Programmer Equipment Chip Unprotect flowchart NO ++n = 1000 FAIL 1. Block Protection Groups are shown in 70/74 START PROTECT ALL GROUPS CURRENT GROUP ...
Page 71
M29DW640F Figure 22. In-System Equipment Group Protect flowchart 1. Block Protection Groups are shown can be either when using the In-System Technique to protect the Extended Block START n = ...
Page 72
Block protection Figure 23. In-System Equipment Chip Unprotect flowchart NO ++n = 1000 YES ISSUE READ/RESET COMMAND FAIL 1. Block Protection Groups are shown in 72/74 START PROTECT ALL GROUPS CURRENT GROUP = ...
Page 73
M29DW640F Revision history Table 33. Document revision history Date 02-Dec-2005 10-Mar-2006 23-Aug-2006 Revision 1.0 First issue. DQ7 changed to DQ7 for Program, Program During Erase Suspend and Program Error in 2.0 Converted to new template. Updated address values in data. ...
Page 74
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...