CY7C1471V33-117AXC Cypress Semiconductor Corp, CY7C1471V33-117AXC Datasheet
CY7C1471V33-117AXC
Specifications of CY7C1471V33-117AXC
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CY7C1471V33-117AXC Summary of contents
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... For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05288 Rev. *I 72-Mbit (2M x 36/4M x 18/1M x 72) Functional Description The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are 3.3V 36/4M x 18/ Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states ...
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... Logic Block Diagram – CY7C1471V33 (2M x 36) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN ADV/ READ LOGIC CE1 CE2 CE3 ZZ CONTROL Logic Block Diagram – CY7C1473V33 (4M x 18) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN ADV/ CE1 CE2 CE3 SLEEP ZZ CONTROL Document #: 38-05288 Rev A1' ...
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... A0, A1, A REGISTER 0 MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ READ LOGIC CE1 CE2 CE3 Sleep ZZ Control Document #: 38-05288 Rev A1 A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY WRITE CONTROL LOGIC DRIVERS CY7C1471V33 CY7C1473V33 CY7C1475V33 MEMORY ARRAY ...
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... Pin Configurations DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP 30 D Document #: 38-05288 Rev. *I 100-pin TQFP Pinout CY7C1471V33 CY7C1471V33 CY7C1473V33 CY7C1475V33 80 DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP A Page ...
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... Pin Configurations (continued DDQ DDQ BYTE DDQ DQP DDQ Document #: 38-05288 Rev. *I 100-pin TQFP Pinout CY7C1473V33 CY7C1471V33 CY7C1473V33 CY7C1475V33 DDQ DQP DDQ BYTE DDQ DDQ Page ...
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... DDQ DDQ N DQP DDQ P NC/144M MODE NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE A A Document #: 38-05288 Rev. *I 165-ball FBGA ( 1.4 mm) Pinout CY7C1471V33 ( CEN CLK TDI A1 TDO TCK TMS CY7C1473V33 (4M x 18) ...
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... DDQ DD DD DDQ DDQ DDQ DDQ DDQ MODE TDI CY7C1471V33 CY7C1473V33 CY7C1475V33 DQb DQb 3 BWS BWS DQb DQb b f BWS BWS DQb DQb DQb DQb DQPf DQPb DDQ DDQ V DQf V DQf DQf DQf DDQ DDQ V V DQf SS SS DQf V V DDQ ...
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... CE to select/deselect the device and CE to select/deselect the device and CE to select/deselect the device and DQP s is controlled CY7C1471V33 CY7C1473V33 CY7C1475V33 are placed in a tri-state condition.The correspondingly left floating selects DD through a pull up DD Page ...
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... When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be tri-stated immediately. Burst Read Accesses The CY7C1471V33, CY7C1473V33 and CY7C1475V33 have an on-chip burst counter that allows the user the ability to Document #: 38-05288 Rev. *I Description . This pin is not available on TQFP packages. ...
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... Burst Write Accesses The CY7C1471V33, CY7C1473V33, and CY7C1475V33 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write opera- tions without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above ...
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... Write Cycle (Continue Burst) Next NOP/Write Abort (Begin Burst) None Write Abort (Continue Burst) Next Ignore Clock Edge (Stall) Current Sleep Mode None [ Truth Table for Read/Write Function (CY7C1471V33) Read Write No bytes written Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Byte C – ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1471V33, CY7C1473V33, and CY7C1475V33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... TAP controller’s capture set-up plus hold time (t plus portion of The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue still CY7C1471V33 CY7C1473V33 CY7C1475V33 Unlike the SAMPLE/PRELOAD Page ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE UNDEFINED [10, 11] Over the Operating Range Description / ns CY7C1471V33 CY7C1473V33 CY7C1475V33 TDOV t TDOX Min. Max Page Unit ...
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... DDQ GND < V < DDQ CY7C1473V33 CY7C1475V33 (2Mx36) (4Mx18) (1Mx72) 000 000 000 01011 01011 01011 001001 001001 001001 100100 010100 110100 00000110100 00000110100 CY7C1471V33 CY7C1473V33 CY7C1475V33 to 2.5V SS 1.25V 50Ω 50Ω 20pF O Min. Max. Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V ...
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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05288 Rev. *I Bit Size (x36) Bit Size (x18 Description CY7C1471V33 CY7C1473V33 CY7C1475V33 Bit Size (x72 110 Page ...
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... L10 59 B8 K11 60 A7 165-Ball ID Bit # 165-Ball L10 P6 28 K10 R6 29 J10 R8 30 H11 P3 31 G11 P4 32 F11 P8 33 E11 P9 34 D11 P10 35 C11 R9 36 A11 R10 37 A9 R11 38 B9 M10 39 A10 CY7C1471V33 CY7C1473V33 CY7C1475V33 Bit # 165-Ball Bit # 165-Ball ID 40 B10 ...
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... J11 V5 72 J10 U5 73 H11 U6 74 H10 W7 75 G11 V7 76 G10 U7 77 F11 V8 78 F10 V9 79 E10 W11 80 E11 W10 81 D11 V11 82 D10 V10 83 C11 U11 84 C10 CY7C1471V33 CY7C1473V33 CY7C1475V33 Bit # 209-Ball ID 85 B11 86 B10 87 A11 88 A10 100 B3 101 C3 102 C4 103 ...
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... V – inputs static /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < CY7C1471V33 CY7C1473V33 CY7C1475V33 Ambient Temperature 0°C to +70°C 3.3V –5%/+10% 2.5V – –40°C to +85°C Min. Max. 3.135 3.6 3.135 ...
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... EIA/JESD51 317Ω 3.3V V OUTPUT GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE CY7C1471V33 CY7C1473V33 CY7C1475V33 165 FBGA 209 BGA Package Package 100 TQFP 165 FBGA 209 FBGA Max ...
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... V is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1471V33 CY7C1473V33 CY7C1475V33 133 MHz 117 MHz Max. Min. Max ...
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... CLZ D(A2) D(A2+1) Q(A3) Q(A4) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1471V33 CY7C1473V33 CY7C1475V33 OEV t CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) ...
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... CDV t DOH t CLZ D(A2) D(A2+1) Q(A3) Q(A4) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED CY7C1471V33 CY7C1473V33 CY7C1475V33 OEV t CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH t OELZ WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) Page ...
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... Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device. 28. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05288 Rev DDZZ High-Z DON’T CARE CY7C1471V33 CY7C1473V33 CY7C1475V33 t ZZREC t RZZI DESELECT or READ Only Page ...
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... Fine-Pitch Ball Grid Array ( 1.4 mm) Lead-Free CY7C1473V33-133BZXI CY7C1475V33-133BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1475V33-133BGXI 117 CY7C1471V33-117AXC 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1473V33-117AXC CY7C1471V33-117BZC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1473V33-117BZC CY7C1471V33-117BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Lead-Free ...
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... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0.20 MAX. 3. DIMENSIONS IN MILLIMETERS A CY7C1471V33 CY7C1473V33 CY7C1475V33 1.40±0.05 12°±1° SEE DETAIL (8X) 0 ...
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... Package Diagrams (continued) TOP VIEW PIN 1 CORNER SEATING PLANE C Document #: 38-05288 Rev. *I 165-ball FBGA ( 1.4 mm) (51-85165 CY7C1471V33 CY7C1473V33 CY7C1475V33 PIN 1 CORNER BOTTOM VIEW Ø0. Ø0. Ø0.45±0.05(165X 1.00 5.00 10.00 B 15.00±0.10 0.15(4X) 51-85165-*A Page ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 209-ball FBGA ( 1.76 mm) (51-85167) CY7C1471V33 CY7C1473V33 CY7C1475V33 ...
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... Document History Page Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Document #: 38-05288 REV. ECN NO. Issue Date ** 114675 08/06/02 *A 121521 02/07/03 *B 223721 See ECN *C 235012 See ECN *D 243572 See ECN *E 299511 See ECN *F 320197 See ECN ...