CY7C056V-12AXC Cypress Semiconductor Corp, CY7C056V-12AXC Datasheet - Page 16

• Manufacturer Part Number: CY7C056V-12AXC
• Description: IC SRAM 576KBIT 12NS 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C056V-12AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 576K (16K x 36)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Density: 576Kb
• Access Time (max): 12ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 14b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 385mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 16K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-06055 Rev. *E
Switching Waveforms
CE
CE
Right Address Valid First:
Left Address Valid First:
Note
44. If t
ADDRESS
ADDRESS
L
R
ADDRESS
Valid First:
ADDRESS
ADDRESS
ADDRESS
CE
CE
Valid First:
CE
CE
PS
0L
0R
0L
0R
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
BUSY
BUSY
BUS
, CE
BUSY
, CE
, CE
, CE
L,R
L,R
R
1L
1L
1R
1R
L
R
R
R
R
L
L
Busy Timing Diagram No. 2 (Address Arbitration)
(continued)
t
t
PS
PS
ADDRESS MATCH
ADDRESS MATCH
Busy Timing Diagram No. 1 (CE Arbitration)
t
t
RC
RC
or t
or t
t
t
PS
PS
WC
WC
t
t
BLA
BLA
CHIP SELECT VALID
CHIP SELECT VALID
ADDRESS MATCH
ADDRESS MATCH
t
t
BLC
BLC
CHIP SELECT VALID
ADDRESS MISMATCH
ADDRESS MISMATCH
CHIP SELECT VALID
t
t
BHA
BHA
t
t
BHC
BHC
[44]
[44]
CY7C056V
CY7C057V
Page 16 of 26
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