CY7C056V-12AXC Cypress Semiconductor Corp, CY7C056V-12AXC Datasheet - Page 11

• Manufacturer Part Number: CY7C056V-12AXC
• Description: IC SRAM 576KBIT 12NS 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C056V-12AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 576K (16K x 36)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Density: 576Kb
• Access Time (max): 12ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 14b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 385mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 16K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Data Retention Mode
The CY7C056V and CY7C057V are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
Timing
Notes
Document #: 38-06055 Rev. *E
V
t
t
t
t
t
t
t
t
t
t
t
1. Chip Enable (CE)
2. CE must be kept between V
3. The RAM can begin operation >t
CE
21. Test conditions used are Load 1.
22. t
23. CE is LOW when CE
24. CE = V
ICC
BHC
PS
WB
WH
BDD
INS
INR
SOP
SWRD
SPS
SAA
Busy Timing
Interrupt Timing
Semaphore Timing
CC
within V
the power-up and power-down transitions.
minimum operating voltage (3.15 volts).
Parameter
BDD
Parameter
[22]
DR1
is a calculated parameter and is the greater of t
DD
DD
, V
in
to V
= V
[21]
SS
DD
3.15 V
[21]
BUSY HIGH from CE HIGH
Port set-up for priority
R/W LOW after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to data valid
INT set time
INT reset time
SEM flag update pulse (OE or SEM)
SEM flag write to read time
SEM flag contention window
SEM address access time
0
to V
[23]
Data Retention Mode
@ VDD
 V
– 0.2 V.
V
–
Test Conditions
CC
DD
must be held HIGH during data retention,
IL
V
, T
and CE
to V
CC
A
DR
= 25 C. This parameter is guaranteed but not tested.
2.0 V
CC
DD
= 2 V
1
– 0.2 V
V
– 0.2 V and 70% of V
Description
IH
.
3.15 V
RC
Over the Operating Range
[24]
after V
WDD
Max
–t
DD
V
50
PWE
t
IH
RC
reaches the
(actual) or t
DD
Unit
during
A
DDD
[13]
–t
SD
Min
(continued)
11
10
(actual).
–
5
0
–
–
–
5
5
–
-12
Max
12
12
12
12
12
–
–
–
–
–
–
CY7C056V
CY7C057V
Min
13
10
–
5
0
–
–
–
5
5
–
-15
Max
15
15
15
15
15
–
–
–
–
–
–
CY7C056V
CY7C057V
Page 11 of 26
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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