CY7C037V-20AXC Cypress Semiconductor Corp, CY7C037V-20AXC Datasheet - Page 8

IC SRAM 576KBIT 20NS 100LQFP

CY7C037V-20AXC

Manufacturer Part Number
CY7C037V-20AXC
Description
IC SRAM 576KBIT 20NS 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C037V-20AXC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
576K (32K x 18)
Speed
20ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C037V-20AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-06078 Rev. *A
Switching Characteristics
Data Retention Mode
The CY7C027V/028V and CY7037V/038V are designed with
battery backup in mind. Data retention voltage and supply cur-
rent are guaranteed over temperature. The following rules en-
sure data retention:
1. Chip enable (CE) must be held HIGH during data retention, with-
2. CE must be kept between V
3. The RAM can begin operation >t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
HD
HZWE
LZWE
WDD
DDD
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
INS
INR
SOP
SWRD
SPS
SAA
Busy Timing
Interrupt Timing
Semaphore Timing
in V
during the power-up and power-down transitions.
imum operating voltage (3.0 volts).
Parameter
[18]
[41]
[41]
[14 ,15]
CC
[14, 15]
to V
CC
[16]
– 0.2V.
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
[16]
CC
Description
– 0.2V and 70% of V
Over the Operating Range
RC
after V
CC
reaches the min-
CC
[11]
(continued)
Min.
13
10
0
3
5
0
5
5
Timing
V
CE
ICC
16. For information on port-to-port delay through RAM cells from writing port
17. Test conditions used are Load 1.
18. t
19. CE = V
CC
-15
Parameter
DR1
to reading port, refer to Read Timing with Busy waveform.
(actual).
but not tested.
BDD
Max.
10
30
25
15
15
15
15
15
15
15
15
is a calculated parameter and is the greater of t
CC
, V
in
CY7C037V/038V
= GND to V
Min.
15
10
0
3
5
0
5
5
3.0V
@ VCC
Data Retention Mode
Test Conditions
V
-20
CC
V
CC
Max.
to V
CC
12
40
30
20
20
20
16
20
20
20
20
DR
, T
> 2.0V
CC
A
= 2V
= 25° C. This parameter is guaranteed
– 0.2V
CY7C027V/028V
CY7C037V/038V
Min.
17
12
0
3
5
0
5
5
[19]
3.0V
WDD
-25
–t
PWE
Max.
15
50
35
20
20
20
17
25
20
20
25
Max.
50
(actual) or t
Page 8 of 18
V
t
IH
RC
Unit
DDD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µA
–t
SD
[+] Feedback

Related parts for CY7C037V-20AXC