M25P40-VMN6P NUMONYX, M25P40-VMN6P Datasheet - Page 8
![IC FLASH 4MBIT 50MHZ 8SOIC](/photos/7/30/73033/m25p40-vmn6p_sml.jpg)
M25P40-VMN6P
Manufacturer Part Number
M25P40-VMN6P
Description
IC FLASH 4MBIT 50MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Specifications of M25P40-VMN6P
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Memory Configuration
512K X 8
Ic Interface Type
Serial, SPI
Clock Frequency
50MHz
Supply Voltage Range
2.3V To 3.6V
Memory Case Style
SOIC
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-3598
497-3598
497-3598
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M25P40-VMN6P
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P40-VMN6PB
Manufacturer:
ST
Quantity:
102
Part Number:
M25P40-VMN6PB
Manufacturer:
ST
Quantity:
20 000
Part Number:
M25P40-VMN6PBA
Manufacturer:
MICRON
Quantity:
20 000
2
2.1
2.2
2.3
2.4
2.5
2.6
8/61
Signal description
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data output (Q) is at high
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress,
the device will be in the Standby Power mode (this is not the Deep Power-down mode).
Driving Chip Select (S) Low selects the device, placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against program or erase instructions (as specified by the values in the BP2, BP1
and BP0 bits of the Status Register).