M25P10-AVMN6T STMicroelectronics, M25P10-AVMN6T Datasheet - Page 33

• Manufacturer Part Number: M25P10-AVMN6T
• Description: IC FLASH 1MBIT 40MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M25P10-AVMN6T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-1622-2

M25P10-A
7
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while V
than the Power On Reset (POR) threshold voltage, V
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of
t
correct operation of the device is not guaranteed if, by this time, V
No Write Status Register, Program or Erase instructions should be sent until the later of:
These values are specified in
If the delay, t
selected for read instructions even if the t
At power-up, the device is in the following state:
Normal precautions must be taken for supply rail decoupling, to stabilize the V
Each device in a system should have the V
the package pins. (Generally, this capacitor is of the order of 0.1 µF).
At power-down, when V
(POR) threshold voltage, V
to any instruction (the designer needs to be aware that if a power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result).
PUW
V
V
t
t
The device is in the Standby mode (not the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
The Write In Progress (WIP) bit is reset.
has elapsed after the moment that V
PUW
VSL
CC
SS
(min) at power-up, and then for a further delay of t
at power-down
after V
after V
VSL
, has elapsed, after V
CC
CC
passed the V
passed the V
CC
WI
drops from the operating voltage, to below the Power On Reset
, all operations are disabled and the device does not respond
Table
CC
CC
) until V
WI
Section 3: SPI
(min) level
8.
threshold
CC
has risen above V
CC
PUW
CC
CC
reaches the correct value:
rises above the V
rail decoupled by a suitable capacitor close to
delay is not yet fully elapsed.
modes.
WI
– all operations are disabled, and
VSL
CC
(min), the device can be
Power-up and power-down
WI
CC
threshold. However, the
is still below V
CC
CC
supply.
CC
is less
(min).
33/51