M28W640ECB90N6 STMicroelectronics, M28W640ECB90N6 Datasheet
M28W640ECB90N6
Specifications of M28W640ECB90N6
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M28W640ECB90N6 Summary of contents
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... Bottom Device Code, M28W640ECB: 8849h April 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M28W640ECT M28W640ECB 64 Mbit (4Mb x16, Boot Block) 3V Supply Flash Memory Figure 1. Packages FBGA TFBGA48 (ZB) 6.39 x 10.5mm TSOP48 (N) ...
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... TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. TSOP Connections Figure 4. TFBGA Connections (Top view through package Figure 5. Block Addresses Figure 6. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Address Inputs (A0-A21 Data Input/Output (DQ0-DQ15 Chip Enable (E Output Enable (G Write Enable (W Write Protect (WP) ...
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Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M28W640ECT, M28W640ECB PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The command set required to control the memory is consistent with JEDEC standards. M28W640ECT, M28W640ECB The memory is offered in TSOP48 (12 X 20mm) and TFBGA48 (6.39 x 10.5mm, 0.75mm pitch) packages and is supplied with all the bits erased (set to ’1’). ...
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M28W640ECT, M28W640ECB Figure 3. TSOP Connections 6/55 A15 1 48 A14 A13 A12 A11 A10 A9 A8 A21 A20 M28W640ECT M28W640ECB A19 A18 A17 ...
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Figure 4. TFBGA Connections (Top view through package A13 B A14 C A15 D A16 E V DDQ A11 A10 W RP A18 A12 A9 A21 A20 ...
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... KWords 3F0000 00FFFF 32 KWords 008000 007FFF 32 KWords 000000 Note: Also see Appendix A, Tables 24 and 25 for a full listing of the Block Addresses. Figure 6. Protection Register Memory Map 8Ch 85h 84h 81h 80h 8/55 Bottom Boot Block Addresses 3FFFFF 3F8000 3F7FFF Total of 8 ...
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... Register and Protection Register Lock). Reset (RP). The Reset input provides a hard- ware reset of the memory. When Reset the memory is in reset mode: the outputs are high impedance and the current consumption is mini- mized. After Reset all blocks are in the Locked state ...
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... Disable, Standby, Automatic Standby and Re- set. See Table 2, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface ...
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... COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings and verifies the correct execution of the Program and Erase commands. The Pro- ...
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... Read operations output the Status Register con- tent after the programming has started. Program- ming aborts if Reset goes to V cannot be guaranteed when the program opera- tion is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 18, Double Word Pro data integrity ...
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... Read operations output the Status Register con- tent after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure 6, Protection Register Memory Map). Attempting to program a previously protected Protection Regis- M28W640ECT, M28W640ECB ter will result in a Status Register error. The pro- tection of the Protection Register is not reversible ...
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... M28W640ECT, M28W640ECB locked-down) state when the device is reset on power-down. Table. 10 shows the protection sta- tus after issuing a Block Lock-Down command. Table 4. Commands Commands 1st Cycle Op. Add Data Read Memory 1+ Write X Array Read Status 1+ Write X Register Read Electronic 1+ Write X Signature Read CFI Query ...
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Table 6. Read Block Lock Signature Block Status Locked Block Unlocked Block IL IL Locked-Down Block Note Locked-Down Block can be locked "DQ0 = 1" or ...
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M28W640ECT, M28W640ECB Table 8. Program, Erase Times and Program/Erase Endurance Cycles Parameter Word Program Double Word Program Quadruple Word Program Main Block Program Parameter Block Program Main Block Erase Parameter Block Erase Program/Erase Cycles (per Block) Note: 1. Typical time ...
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Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status can- not be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing ...
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M28W640ECT, M28W640ECB Table 10. Protection Status Current (1) Protection Status (WP, DQ1, DQ0) Program/Erase Current State Allowed 1,0,0 yes (2) no 1,0,1 1,1,0 yes 1,1,1 no 0,0,0 yes (2) no 0,0,1 0,1,1 no Note: 1. The lock status is defined ...
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... When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Pro- gram/Erase Resume command. The Erase Suspend Status should only be consid- ered valid when the Program/Erase Controller Sta- tus bit is High (Program/Erase Controller inactive). Bit 7 is set within 30µ ...
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... Controller Status bit is High (Program/ Erase Controller inactive). Bit 2 is set within 5µs of the Program/Erase Suspend command being is- sued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is is- sued the Program Suspend Status bit returns Low. ...
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... Supply Voltage DD DDQ V Program Voltage PP Note: 1. Depends on range. plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter (1) M28W640ECT, M28W640ECB Value Min Max – – ...
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M28W640ECT, M28W640ECB DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC characteristics Tables that follow, are de- rived from ...
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Table 15. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Read) DD Supply Current (Stand- DD1 Automatic Stand-by) Supply Current I DD2 (Reset) I Supply Current (Program) DD3 I ...
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M28W640ECT, M28W640ECB Figure 9. Read AC Waveforms A0-A21 E G DQ0-DQ15 ADDR. VALID CHIP ENABLE Table 16. Read AC Characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ...
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Figure 10. Write AC Waveforms, Write Enable Controlled M28W640ECT, M28W640ECB 25/55 ...
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M28W640ECT, M28W640ECB Table 17. Write AC Characteristics, Write Enable Controlled Symbol Alt t t Write Cycle Time AVAV Address Valid to Write Enable High AVWH Data Valid to Write Enable High DVWH DS t ...
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Figure 11. Write AC Waveforms, Chip Enable Controlled M28W640ECT, M28W640ECB 27/55 ...
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M28W640ECT, M28W640ECB Table 18. Write AC Characteristics, Chip Enable Controlled Symbol Alt t t Write Cycle Time AVAV Address Valid to Chip Enable High AVEH Data Valid to Chip Enable High DVEH DS Chip ...
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Figure 12. Power-Up and Reset AC Waveforms tVDHPH VDD, VDDQ Table 19. Power-Up and Reset AC Characteristics Symbol Parameter t PHWL Reset High to Write Enable Low, Chip t PHEL Enable Low, Output Enable Low t ...
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M28W640ECT, M28W640ECB PACKAGE MECHANICAL Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline 20mm, Package Outline 1 N/2 TSOP-a Note: Drawing is not to scale. Table 20. TSOP48 - 48 lead Plastic Thin Small Outline ...
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Figure 14. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline BALL "A1" Note: Drawing is not to scale. Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data Symbol ...
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M28W640ECT, M28W640ECB Figure 15. TFBGA48 Daisy Chain - Package Connections (Top view through package Figure 16. TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package ...
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PART NUMBERING Table 22. Ordering Information Scheme Example: Device Type M28 Operating Voltage 2.7V to 3.6V 1.65V to 3.6V DD DDQ Device Function 640EC = 64 Mbit (4 Mb x16), Boot Block Array Matrix ...
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... E = Lead-Free Package, Standard Packing F = Lead-Free Package, Tape & Reel Packing Note:Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. ...
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APPENDIX A. BLOCK ADDRESS TABLES Table 24. Top Boot Block Addresses, M28W640ECT Size # Address Range (KWord 3FF000-3FFFFF 1 4 3FE000-3FEFFF 2 4 3FD000-3FDFFF 3 4 3FC000-3FCFFF 4 4 3FB000-3FBFFF 5 4 3FA000-3FAFFF 6 4 3F9000-3F9FFF 7 4 ...
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M28W640ECT, M28W640ECB 84 32 190000-197FFF 85 32 188000-18FFFF 86 32 180000-187FFF 87 32 178000-17FFFF 88 32 170000-177FFF 89 32 168000-16FFFF 90 32 160000-167FFF 91 32 158000-15FFFF 92 32 150000-157FFF 93 32 148000-14FFFF 94 32 140000-147FFF 95 32 138000-13FFFF 96 32 ...
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Table 25. Bottom Boot Block Addresses, M28W640ECB Size # Address Range (KWord) 134 32 3F8000-3FFFFF 133 32 3F0000-3F7FFF 132 32 3E8000-3EFFFF 131 32 3E0000-3E7FFF 130 32 3D8000-3DFFFF 129 32 3D0000-3D7FFF 128 32 3C8000-3CFFFF 127 32 3C0000-3C7FFF 126 32 3B8000-3BFFFF 125 ...
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M28W640ECT, M28W640ECB 46 32 138000-13FFFF 45 32 130000-137FFF 44 32 128000-12FFFF 43 32 120000-127FFF 42 32 118000-11FFFF 41 32 110000-117FFF 40 32 108000-10FFFF 39 32 100000-107FFF 38 32 0F8000-0FFFFF 37 32 0F0000-0F7FFF 36 32 0E8000-0EFFFF 35 32 0E0000-0E7FFF 34 32 ...
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... Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. M28W640ECT, M28W640ECB structure is read from the memory. Tables 26, 27, 28, 29, 30 and 31 show the addresses used to re- trieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is writ- ten (see Table 31, Security Code area) ...
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M28W640ECT, M28W640ECB Table 28. CFI Query System Interface Information Offset Data V Logic Supply Minimum Program/Erase or Write voltage DD 1Bh 0027h V Logic Supply Maximum Program/Erase or Write voltage DD 1Ch 0036h V [Programming] Supply Minimum Program/Erase voltage PP ...
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Table 29. Device Geometry Definition Offset Word Data Mode 27h 0017h Device Size = 2 28h 0001h Flash Device Interface Code description 29h 0000h 2Ah 0003h Maximum number of bytes in multi-byte program or page = 2 2Bh 0000h Number ...
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M28W640ECT, M28W640ECB Table 30. Primary Algorithm-Specific Extended Query Table Offset Data ( 35h (P+0)h = 35h 0050h (P+1)h = 36h 0052h Primary Algorithm extended Query table unique ASCII string “PRI” (P+2)h = 37h 0049h (P+3)h = 38h 0031h ...
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Table 31. Security Code Area Offset Data 80h 00XX Protection Register Lock 81h XXXX 82h XXXX 64 bits: unique device number 83h XXXX 84h XXXX 85h XXXX 86h XXXX 87h XXXX 88h XXXX 128 bits: User Programmable OTP 89h XXXX ...
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... If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 44/55 program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10 writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 Invalid if (status_register ...
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... If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0. double_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (any_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; writeToFlash (addressToProgram2, dataToProgram2) ; /*Memory enters read status state after the Program command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 Invalid if (status_register ...
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... Program command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 Invalid if (status_register.b3==1) /*VPP invalid error */ Error (1, 2) error_handler ( ) ...
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Figure 20. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another address Write D0h Program Continues program_suspend_command ( ) ...
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... Note error is found, the Status Register must be cleared before further Program/Erase operations. 48/55 erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ; writeToFlash (blockToErase, 0xD0 only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */ do { status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 Invalid if (status_register ...
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Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock Write ...
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M28W640ECT, M28W640ECB Figure 23. Locking Operations Flowchart and Pseudo Code Start Write 60h Write 01h, D0h or 2Fh Write 90h Read Block Lock States Locking change confirmed? YES Write FFh End 50/55 locking_operation_command (address, lock_operation) { writeToFlash (any_address, 0x60) ; ...
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... Note: 1. Status check of b1 (Protected Block sequence error is found, the Status Register must be cleared before further Program/Erase Controller operations. protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ; writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 ...
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M28W640ECT, M28W640ECB APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE Table 32. Write State Machine Current/Next, sheet Data Current SR Read When State bit 7 Array Read (FFh) Read Array “1” Array Read Array Prog.Setup Read “1” ...
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Table 33. Write State Machine Current/Next, sheet Current State Read Elect.Sg. (90h) Read Array Read Elect.Sg. Read CFI Query Read Status Read Elect.Sg. Read CFI Query Read Elect.Sg. Read Elect.Sg. Read CFI Query Read CFI Query Read ...
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... Minimum V voltage changed from 2.7V to 1.65V. Note removed from Figure 6, DDQ Protection Register Memory Map. Note removed from Table 7, Read Protection Register and Lock Register, and DQ2 value changed. “Double Word Program Command” and “Quadruple Word Program Command” paragraphs clarified. ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...