MT41J256M8JE-187E:A Micron Technology Inc, MT41J256M8JE-187E:A Datasheet - Page 141

• Manufacturer Part Number: MT41J256M8JE-187E:A
• Description: IC DDR3 SDRAM 2GBIT 82FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8JE-187E:A

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 533MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 82-FBGA
• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 295mA
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4329252

Mode Register 2 (MR2)
Figure 56: Mode Register 2 (MR2) Definition
CAS Write Latency (CWL)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Notes:
The mode register 2 (MR2) controls additional functions and features not available in
the other mode registers. These additional functions are CAS WRITE latency (CWL), AU-
TO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT
(R
programmed via the MRS command and will retain the stored information until it is
programmed again or until the device loses power. Reprogramming the MR2 register
will not alter the contents of the memory array, provided it is performed correctly. The
MR2 register must be loaded when all banks are idle and no data bursts are in progress,
and the controller must wait the specified time
sequent operation.
CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the
internal write to the latching of the first data in. CWL must be correctly set to the corre-
sponding operating clock frequency (see Figure 56). The overall WRITE latency (WL) is
equal to CWL + AL (Figure 54 (page 137)).
M16
0
0
1
1
TT(WR)
1. MR2[17, 14:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.
2. On die revision A, ASR is not available; MR2[6] must be programmed to a "0," and if
M15
0
1
0
1
operating self refresh mode above 85°C, use SRT, MR2[7].
). These functions are controlled via the bits shown in Figure 56. The MR2 is
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
M10
Mode Register
0
0
1
1
M9
0
1
0
1
R
Dynamic ODT
TT(WR)
BA2
0
17
Reserved
(R
1
RZQ/4
RZQ/2
TT(WR)
BA1
16
1
disabled
)
0
BA0
15
0
14
A14
1
141
0
13
M7
A13
1
0
1
0
12
Self Refresh Temperature
A12 A11
Extended (0°C to 95°C)
1
M6
Normal (0°C to 85°C)
0
1
0
11
Enabled: Automatic
1
Disabled: Manual
Auto Self Refresh
R
Micron Technology, Inc. reserves the right to change products or specifications without notice.
10
TT(WR)
(Optional)
A10
9
A9
0
1
8
A8
2Gb: x4, x8, x16 DDR3 SDRAM
SRT
t
MRD and
7
A7 A6 A5 A4 A3
ASR
6
2
M5
0
0
0
0
1
1
1
1
5
CWL
M4
0
0
1
1
0
0
1
1
4
Mode Register 2 (MR2)
M3
0
1
0
1
0
1
0
1
t
MOD before initiating a sub-
3
6 CK (2.5ns > t CK ≥ 1.875ns)
7 CK (1.875ns > t CK ≥ 1.5ns)
9 CK (1.25ns > t CK ≥ 1.07ns)
0
8 CK (1.5ns > t CK ≥ 1.25ns)
2
1
CAS Write Latency (CWL)
© 2006 Micron Technology, Inc. All rights reserved.
A2 A1 A0
0
5 CK ( t CK ≥ 2.5ns)
1
1
0
Reserved
Reserved
Reserved
1
0
Address bus
Mode register 2 (MR2)