IS62C256-70U ISSI, Integrated Silicon Solution Inc, IS62C256-70U Datasheet - Page 7
IS62C256-70U
Manufacturer Part Number
IS62C256-70U
Description
IC SRAM 256KBIT 70NS 28SOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS62C256-70U.pdf
(8 pages)
Specifications of IS62C256-70U
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
256K (32K x 8)
Speed
70ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Price
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AC WAVEFORMS
WRITE CYCLE NO. 2
WRITE CYCLE NO. 3
IS62C256
Notes:
1. The internal write time is defined by the overlap of
2. I/O will assume the High-Z state if
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
ADDRESS
ADDRESS
D
D
OUT
WE
D
OE
CS
OUT
WE
D
OE
IN
CS
IN
LOW
LOW
LOW
t
SA
(
(
DATA UNDEFINED
OE
OE
t
DATA UNDEFINED
SA
is HIGH During Write Cycle)
is LOW During Write Cycle)
OE
= V
IH
.
VALID ADDRESS
t
t
Cs
AW
t
t
HZWE
AW
HZWE
LOW and
VALID ADDRESS
t
t
PWE1
WC
t
t
PWE2
WC
(1)
(1,2)
WE
HIGH-Z
HIGH-Z
LOW. All signals must be in valid states to initiate a Write,
t
SD
t
DATA
SD
DATA
IN
IN
VALID
VALID
t
HD
t
t
HD
LZWE
t
LZWE
t
HA
t
HA
CS_WR2.eps
CS_WR3.eps
ISSI
®
7