IS25C04-2ZI-TR ISSI, Integrated Silicon Solution Inc, IS25C04-2ZI-TR Datasheet - Page 5

• Manufacturer Part Number: IS25C04-2ZI-TR
• Description: IC EEPROM 4KBIT 10MHZ 8TSSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS25C04-2ZI-TR

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 2MHz, 5MHz, 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DEVICE OPERATION
The operations of the IS25C02/04 are controlled by a set of instructions that are clocked-in serially SI pin. (See Table
3). To begin an instruction, the chip select (CS) should be dropped Low. Subsequently, each Low-to-High transition of
the clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to continue to input
an address or data to SI, or to output data from SO. During data output, values appear on the falling edge of SK. All
bits are transferred with MSB first. Upon the last bit of communication, but prior to any following Low-to-High transition
of SK, CS should be raised High to end the transaction. The device then would enter Standby Mode if no internal
programming were underway.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Preliminary Information Rev. 00F
12/22/05
Table 3. Instruction Set
Name
WREN
WRDI
RDSR
WRSR
READ
WRITE 0000 A 8 010
WRITE ENABLE (WREN)
When Vcc is initially applied, the device powers up with
both status register and entire array in a write-disabled
state. Upon completion of Write Disable (WRDI), Write
Status Register (WRSR), or Write Data to Array
(WRITE), the device resets the WEN bit in the Status
Register to 0. Prior to any data modification, a WREN
instruction is necessary to set WEN to 1. (See Figure 2
for timing).
WRITE DISABLE (WRDI)
The device can be completely protected from modifica-
tion by resetting WEN to 0 through the WRDI instruc-
tion. (See Figure 3 for timing).
IS25C02
IS25C04
1. X = Don’t care bit. For consistency, it is best to use “0”.
2. Some address bits are don’t care. See Table 5.
3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon CS going High there is no
affect. A valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the
array or Status Register to be ignored.
0000 A 8 011
0000 X110
0000 X100
0000 X101
0000 X001
Op-code
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Array
Write Data to Array
Operation
Address
A 7 -A 0
A 7 -A 0
-
-
-
-
READ STATUS REGISTER (RDSR)
The Read Status instruction indicates the status of the
Block Protection setting (see Table 2), the Write Enable
state, and the RDY status. RDSR is the only instruc-
tion accepted when a write cycle is underway. It is
recommended that the status of RDY be checked,
especially prior to an attempted modification of data.
The 8 bits of the Status Register can be repeatedly
output on SO after the initial Op-code. (See Figure 4 for
timing).
Data(SI)
D 7 -D 0
D 7 -D 0 ,...
-
-
-
-
Data (SO)
D 7 -D 0 ,...
D 7 -D 0 ,...
-
-
-
-
ISSI
®
5